From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 22 May 2021 11:27:17 +0000 (+0100)
Subject: rename vco_test_ana to pll_testout_o
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e4ffa78b6ca6cc9ed8d0407c4a73394991003663;p=libresoc-litex.git

rename vco_test_ana to pll_testout_o
---

diff --git a/libresoc/core.py b/libresoc/core.py
index 681ccf6..478bcaf 100644
--- a/libresoc/core.py
+++ b/libresoc/core.py
@@ -275,7 +275,7 @@ class LibreSoC(CPU):
             self.pll_ana_o = Signal()
             self.cpu_params['i_clk_sel_i'] = self.clk_sel
             self.cpu_params['o_pll_18_o'] = self.pll_18_o
-            self.cpu_params['o_vco_test_ana'] = self.pll_ana_o
+            self.cpu_params['o_pll_testout_o'] = self.pll_ana_o
 
         # add wishbone buses to cpu params
         self.cpu_params.update(make_wb_bus("ibus", ibus, True))