From: Timothy M. Jones <tjones1@inf.ed.ac.uk>
Date: Thu, 22 Jul 2010 17:52:02 +0000 (+0100)
Subject: O3CPU: Fix a bug where stores in the cpu where never marked as split.
X-Git-Tag: stable_2012_02_02~984
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e50a880297f13817200f4e74272ad1cf3194d401;p=gem5.git

O3CPU: Fix a bug where stores in the cpu where never marked as split.
---

diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
index cf51f8eab..7b8b1e2e3 100644
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -822,6 +822,12 @@ LSQUnit<Impl>::write(Request *req, Request *sreqLow, Request *sreqHigh,
     storeQueue[store_idx].sreqLow = sreqLow;
     storeQueue[store_idx].sreqHigh = sreqHigh;
     storeQueue[store_idx].size = sizeof(T);
+
+    // Split stores can only occur in ISAs with unaligned memory accesses.  If
+    // a store request has been split, sreqLow and sreqHigh will be non-null.
+    if (TheISA::HasUnalignedMemAcc && sreqLow) {
+        storeQueue[store_idx].isSplit = true;
+    }
     assert(sizeof(T) <= sizeof(storeQueue[store_idx].data));
 
     T gData = htog(data);