From: Andrew Waterman <waterman@eecs.berkeley.edu>
Date: Fri, 7 Feb 2014 09:15:49 +0000 (-0800)
Subject: Clear EVEC LSBs, which kindly prevents a segfault
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e50ddde0fff514abb621d72e935d7f0970469eae;p=riscv-isa-sim.git

Clear EVEC LSBs, which kindly prevents a segfault
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index 05fee79..ed19509 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -243,8 +243,8 @@ reg_t processor_t::set_pcr(int which, reg_t val)
     case CSR_EPC:
       state.epc = val;
       break;
-    case CSR_EVEC: 
-      state.evec = val;
+    case CSR_EVEC:
+      state.evec = val & ~3;
       break;
     case CSR_CYCLE:
     case CSR_TIME: