From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 28 Oct 2018 15:24:07 +0000 (+0000)
Subject: adjust mmu load to take reg_spec_t so that proper offset-adjustments can be made
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e50e079449d075cbfd047ce0139f00e639d1bca6;p=riscv-isa-sim.git

adjust mmu load to take reg_spec_t so that proper offset-adjustments can be made

the adding of the immediate plus the relevant offset to the relevant
register needs to be calculated before the load takes place.  algorithm
is slightly different from the one used in rv_add
---

diff --git a/riscv/insns/c_fld.h b/riscv/insns/c_fld.h
index 273e8c1..5ff7109 100644
--- a/riscv/insns/c_fld.h
+++ b/riscv/insns/c_fld.h
@@ -1,4 +1,4 @@
 require_extension('C');
 require_extension('D');
 require_fp;
-WRITE_RVC_FRS2S(f64(MMU.load_uint64(rv_add(RVC_RS1S, insn.rvc_ld_imm()))));
+WRITE_RVC_FRS2S(f64(MMU.load_uint64(insn.rvc_rs1s(), insn.rvc_ld_imm()))); //RVC_RS1S
diff --git a/riscv/insns/c_flw.h b/riscv/insns/c_flw.h
index efe1c86..7e87c43 100644
--- a/riscv/insns/c_flw.h
+++ b/riscv/insns/c_flw.h
@@ -2,7 +2,7 @@ require_extension('C');
 if (xlen == 32) {
   require_extension('F');
   require_fp;
-  WRITE_RVC_FRS2S(f32(MMU.load_uint32(rv_add(RVC_RS1S, insn.rvc_lw_imm()))));
+  WRITE_RVC_FRS2S(f32(MMU.load_uint32(insn.rvc_rs1s(), insn.rvc_lw_imm()))); //RVC_RS1S
 } else { // c.ld
-  WRITE_RVC_RS2S(MMU.load_int64(rv_add(RVC_RS1S, insn.rvc_ld_imm())));
+  WRITE_RVC_RS2S(MMU.load_int64(insn.rvc_rs1s(), insn.rvc_ld_imm())); //RVC_RS1S
 }
diff --git a/riscv/insns/c_lw.h b/riscv/insns/c_lw.h
index d08bab5..40db006 100644
--- a/riscv/insns/c_lw.h
+++ b/riscv/insns/c_lw.h
@@ -1,2 +1,2 @@
 require_extension('C');
-WRITE_RVC_RS2S(MMU.load_int32(rv_add(RVC_RS1S, insn.rvc_lw_imm())));
+WRITE_RVC_RS2S(MMU.load_int32(insn.rvc_rs1s(), insn.rvc_lw_imm())); // RVC_RS1S
diff --git a/riscv/insns/fld.h b/riscv/insns/fld.h
index c63fdd8..d275129 100644
--- a/riscv/insns/fld.h
+++ b/riscv/insns/fld.h
@@ -1,3 +1,3 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(f64(MMU.load_uint64(rv_add(RS1, insn.i_imm()))));
+WRITE_FRD(f64(MMU.load_uint64(insn.rs1(), insn.i_imm()))); // RS1
diff --git a/riscv/insns/flq.h b/riscv/insns/flq.h
index 0e371ef..6776271 100644
--- a/riscv/insns/flq.h
+++ b/riscv/insns/flq.h
@@ -1,3 +1,3 @@
 require_extension('Q');
 require_fp;
-WRITE_FRD(MMU.load_float128(rv_add(RS1, insn.i_imm())));
+WRITE_FRD(MMU.load_float128(rv_add(RS1, insn.i_imm()))); // XXX TODO: adjust to SV
diff --git a/riscv/insns/flw.h b/riscv/insns/flw.h
index 301b9b2..4659e4b 100644
--- a/riscv/insns/flw.h
+++ b/riscv/insns/flw.h
@@ -1,3 +1,3 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(f32(MMU.load_uint32(rv_add(RS1, insn.i_imm()))));
+WRITE_FRD(f32(MMU.load_uint32(insn.rs1(), insn.i_imm()))); // RS1
diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
index 61e44da..aa5a883 100644
--- a/riscv/insns/lb.h
+++ b/riscv/insns/lb.h
@@ -1 +1 @@
-WRITE_RD(MMU.load_int8(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_int8(insn.rs1(), insn.i_imm())); // RS1
diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
index 2165875..04d954a 100644
--- a/riscv/insns/lbu.h
+++ b/riscv/insns/lbu.h
@@ -1 +1 @@
-WRITE_RD(MMU.load_uint8(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_uint8(insn.rs1(), insn.i_imm())); // RS1
diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
index 6349603..50249be 100644
--- a/riscv/insns/ld.h
+++ b/riscv/insns/ld.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(MMU.load_int64(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_int64(insn.rs1(), insn.i_imm())); // RS1
diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
index 0ac4b9a..9c44519 100644
--- a/riscv/insns/lh.h
+++ b/riscv/insns/lh.h
@@ -1 +1 @@
-WRITE_RD(MMU.load_int16(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_int16(insn.rs1(), insn.i_imm())); // RS1
diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
index b428ffa..8d5167b 100644
--- a/riscv/insns/lhu.h
+++ b/riscv/insns/lhu.h
@@ -1 +1 @@
-WRITE_RD(MMU.load_uint16(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_uint16(insn.rs1(), insn.i_imm())); // RS1
diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
index 45e082a..d33625f 100644
--- a/riscv/insns/lw.h
+++ b/riscv/insns/lw.h
@@ -1 +1 @@
-WRITE_RD(MMU.load_int32(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_int32(insn.rs1(), insn.i_imm())); // RS1
diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
index f0e46a2..bde9c07 100644
--- a/riscv/insns/lwu.h
+++ b/riscv/insns/lwu.h
@@ -1,2 +1,2 @@
 require_rv64;
-WRITE_RD(MMU.load_uint32(rv_add(RS1, insn.i_imm())));
+WRITE_RD(MMU.load_uint32(insn.rs1(), insn.i_imm())); // RS1
diff --git a/riscv/sv_mmu.cc b/riscv/sv_mmu.cc
index fa20651..829e39f 100644
--- a/riscv/sv_mmu.cc
+++ b/riscv/sv_mmu.cc
@@ -1,6 +1,12 @@
 #include "sv_mmu.h"
 
 #define sv_load_func(type, ext) \
+sv_reg_t sv_mmu_t::load_##type(reg_spec_t const& spec, sv_reg_t const& offs) { \
+  reg_t reg = proc->s.READ_REG(spec); \
+  sv_reg_t addr = proc->s.rv_add(reg, offs); \
+  type##_t v = mmu_t::load_##type(addr); \
+  return proc->s.adjust_load(sv_reg_t(v), sizeof(type##_t), ext); \
+} \
 sv_reg_t sv_mmu_t::load_##type(reg_t const& addr) { \
   type##_t v = mmu_t::load_##type(addr); \
   return proc->s.adjust_load(sv_reg_t(v), sizeof(type##_t), ext); \
diff --git a/riscv/sv_mmu.h b/riscv/sv_mmu.h
index 7101ba4..824d166 100644
--- a/riscv/sv_mmu.h
+++ b/riscv/sv_mmu.h
@@ -13,6 +13,7 @@ public:
   sv_mmu_t(simif_t* sim, processor_t* proc) : mmu_t(sim, proc) {}
 
   #define sv_load_func_decl(type) \
+    sv_reg_t load_##type(reg_spec_t const& reg, sv_reg_t const& offs); \
     sv_reg_t load_##type(reg_t const& addr);
 
   // load value from memory at aligned address; zero extend to register width