From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Mon, 14 Aug 2017 23:28:59 +0000 (-0700)
Subject: Fixed bug in GP_COUNTx model
X-Git-Tag: yosys-0.8~344^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e5109847c9a6c4b34a2d78442758773adfea2f4f;p=yosys.git

Fixed bug in GP_COUNTx model
---

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index 84a5dd049..5d9d67750 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -147,10 +147,11 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 
 					if(KEEP) begin
 					end
-					else if(UP)
+					else if(UP) begin
 						count		<= count + 1'd1;
 						if(count == 14'h3fff)
 							count	<= COUNT_TO;
+					end
 					else begin
 						count		<= count - 1'd1;
 
@@ -174,10 +175,11 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 
 					if(KEEP) begin
 					end
-					else if(UP)
+					else if(UP) begin
 						count		<= count + 1'd1;
 						if(count == 14'h3fff)
 							count	<= COUNT_TO;
+					end
 					else begin
 						count		<= count - 1'd1;
 
@@ -218,10 +220,11 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
 
 						if(KEEP) begin
 						end
-						else if(UP)
+						else if(UP) begin
 							count		<= count + 1'd1;
 							if(count == 14'h3fff)
 								count	<= COUNT_TO;
+						end
 						else begin
 							count		<= count - 1'd1;
 
@@ -284,10 +287,11 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 					//Main counter
 					if(KEEP) begin
 					end
-					else if(UP)
+					else if(UP) begin
 						count		<= count + 1'd1;
 						if(count == 8'hff)
 							count	<= COUNT_TO;
+					end
 					else begin
 						count		<= count - 1'd1;
 
@@ -312,10 +316,11 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 					//Main counter
 					if(KEEP) begin
 					end
-					else if(UP)
+					else if(UP) begin
 						count		<= count + 1'd1;
 						if(count == 8'hff)
 							count	<= COUNT_TO;
+					end
 					else begin
 						count		<= count - 1'd1;
 
@@ -356,17 +361,17 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
 
 						if(KEEP) begin
 						end
-						else if(UP)
+						else if(UP) begin
 							count		<= count + 1'd1;
 							if(count == 8'hff)
 								count	<= COUNT_TO;
+						end
 						else begin
 							count		<= count - 1'd1;
 
 							if(count == 0)
 								count	<= COUNT_TO;
 						end
-
 					end
 
 				end