From: Shriya Sharma <shriya@redsemiconductor.com>
Date: Tue, 26 Sep 2023 11:02:17 +0000 (+0100)
Subject: Added brackets for lhzx instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e512dc75b16c579dcf9174d890fff2187b39aedd;p=openpower-isa.git

Added brackets for lhzx instruction
---

diff --git a/openpower/isa/fixedload.mdwn b/openpower/isa/fixedload.mdwn
index 649fa04c..30bcb3ef 100644
--- a/openpower/isa/fixedload.mdwn
+++ b/openpower/isa/fixedload.mdwn
@@ -160,7 +160,7 @@ Description:
 
     Let the effective address (EA) be the sum
     (RA|0)+ (RB). The halfword in storage addressed by
-    EA is loaded into RT 48:63. RT 0:47 are set to 0.
+    EA is loaded into RT[48:63]. RT 0:47 are set to 0.
 
 Special Registers Altered: