From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 14 May 2021 18:53:52 +0000 (+0100)
Subject: add FRA-FRT fp reg names to ISACaller parser
X-Git-Tag: 0.0.3~45
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e524357b8a641396bb3d50bcef4973d923648571;p=openpower-isa.git

add FRA-FRT fp reg names to ISACaller parser
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 9ce9905b..4b8c1004 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -54,6 +54,11 @@ special_sprs = {
 REG_SORT_ORDER = {
     # TODO (lkcl): adjust other registers that should be in a particular order
     # probably CA, CA32, and CR
+    "FRT": 0,
+    "FRA": 0,
+    "FRB": 0,
+    "FRC": 0,
+    "FRS": 0,
     "RT": 0,
     "RA": 0,
     "RB": 0,
diff --git a/src/openpower/decoder/pseudo/parser.py b/src/openpower/decoder/pseudo/parser.py
index 0e671960..dce89121 100644
--- a/src/openpower/decoder/pseudo/parser.py
+++ b/src/openpower/decoder/pseudo/parser.py
@@ -23,6 +23,8 @@ import ast
 
 # Helper function
 
+regs = ['RA', 'RS', 'RB', 'RC', 'RT']
+fregs = ['FRA', 'FRS', 'FRB', 'FRC', 'FRT']
 
 def Assign(autoassign, assignname, left, right, iea_mode):
     names = []
@@ -263,7 +265,7 @@ class PowerParser:
         print(form)
         formkeys = form._asdict().keys()
         self.declared_vars = set()
-        for rname in ['RA', 'RB', 'RC', 'RT', 'RS']:
+        for rname in regs + fregs:
             self.gprs[rname] = None
             self.declared_vars.add(rname)
         self.available_op_fields = set()
@@ -673,7 +675,7 @@ class PowerParser:
             p[0] = apply_trailer(p[1], p[2])
             if isinstance(p[1], ast.Name):
                 name = p[1].id
-                if name in ['RA', 'RS', 'RB', 'RC', 'RT']:
+                if name in regs + fregs:
                     self.read_regs.add(name)
 
     def p_atom_name(self, p):