From: lkcl <lkcl@web>
Date: Thu, 26 May 2022 17:03:59 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2073
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e528b7204010dab24db0a49ecbf2ff990415c533;p=libreriscv.git

---

diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index b96bb68c4..c8d962985 100644
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -652,7 +652,7 @@ the CR Register, not to individual bits within the CR register.
 
 In OpenPOWER v3.0/1, BF/BT/BA/BB are all 5 bits.  The top 3 bits (0:2)
 select one of the 8 CRs; the bottom 2 bits (3:4) select one of 4 bits
-*in* that CR.  The numbering was determined (after 4 months of
+*in* that CR (EQ/LT/GT/SO).  The numbering was determined (after 4 months of
 analysis and research) to be as follows:
 
     CR_index = 7-(BA>>2)      # top 3 bits but BE
@@ -662,7 +662,7 @@ analysis and research) to be as follows:
     CR_bit = (CR_reg & (1<<bit_index)) != 0
 
 When it comes to applying SV, it is the CR\_reg number to which SV EXTRA2/3
-applies, **not** the CR\_bit portion (bits 3:4):
+applies, **not** the CR\_bit portion (bits 3-4):
 
     if extra3_mode:
         spec = EXTRA3
@@ -678,7 +678,7 @@ applies, **not** the CR\_bit portion (bits 3:4):
        return (spec[1:2] << 5) | BA
 
 Thus, for example, to access a given bit for a CR in SV mode, the v3.0B
-algorithm to determin CR\_reg is modified to as follows:
+algorithm to determine CR\_reg is modified to as follows:
 
     CR_index = 7-(BA>>2)      # top 3 bits but BE
     if spec[0]: