From: Michael Meissner <meissner@gcc.gnu.org>
Date: Wed, 29 Mar 1995 19:38:55 +0000 (+0000)
Subject: Do not move float values through memory to get to/from gp registers if -msoft-float.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e52e05cad74a399b9109ddb61cc9c0c7586ac0c2;p=gcc.git

Do not move float values through memory to get to/from gp registers if -msoft-float.

From-SVN: r9242
---

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index e546a5cb1cd..1b253616ca0 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -3901,11 +3901,11 @@
   [(set_attr "type" "*,*,*,compare,*,*,load,*")
    (set_attr "length" "*,*,12,*,8,*,*,*")])
 
-;; For floating-point, we normally deal with the floating-point registers.
-;; The sole exception is that parameter passing can produce floating-point
-;; values in fixed-point registers.  Unless the value is a simple constant
-;; or already in memory, we deal with this by allocating memory and copying
-;; the value explicitly via that memory location.
+;; For floating-point, we normally deal with the floating-point registers
+;; unless -msoft-float is used.  The sole exception is that parameter passing
+;; can produce floating-point values in fixed-point registers.  Unless the
+;; value is a simple constant or already in memory, we deal with this by
+;; allocating memory and copying the value explicitly via that memory location.
 (define_expand "movsf"
   [(set (match_operand:SF 0 "nonimmediate_operand" "")
 	(match_operand:SF 1 "any_operand" ""))]
@@ -3923,70 +3923,73 @@
       && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
     operands[1] = alter_subreg (operands[1]);
 
-  if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
+  if (TARGET_HARD_FLOAT)
     {
-      /* If this is a store to memory or another integer register do the
-	 move directly.  Otherwise store to a temporary stack slot and
-	 load from there into a floating point register.  */
-
-      if (GET_CODE (operands[0]) == MEM
-	  || (GET_CODE (operands[0]) == REG
-	      && (REGNO (operands[0]) < 32
-		  || (reload_in_progress
-		      && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
+      if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
 	{
-	  emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
-			  operand_subword (operands[1], 0, 0, SFmode));
-	  DONE;
-	}
-      else
-	{
-	  rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
-
-	  emit_move_insn (stack_slot, operands[1]);
-	  emit_move_insn (operands[0], stack_slot);
-	  DONE;
+	  /* If this is a store to memory or another integer register do the
+	     move directly.  Otherwise store to a temporary stack slot and
+	     load from there into a floating point register.  */
+
+	  if (GET_CODE (operands[0]) == MEM
+	      || (GET_CODE (operands[0]) == REG
+		  && (REGNO (operands[0]) < 32
+		      || (reload_in_progress
+			  && REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))))
+	    {
+	      emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
+			      operand_subword (operands[1], 0, 0, SFmode));
+	      DONE;
+	    }
+	  else
+	    {
+	      rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
+
+	      emit_move_insn (stack_slot, operands[1]);
+	      emit_move_insn (operands[0], stack_slot);
+	      DONE;
+	    }
 	}
-    }
 
-  if (GET_CODE (operands[0]) == MEM)
-    {
-      /* If operands[1] is a register, it may have double-precision data
-	 in it, so truncate it to single precision.  We need not do
-	 this for POWERPC.  */
-      if (! TARGET_POWERPC && TARGET_HARD_FLOAT && GET_CODE (operands[1]) == REG)
+      if (GET_CODE (operands[0]) == MEM)
 	{
-	  rtx newreg = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
-	  emit_insn (gen_truncdfsf2 (newreg,
-				     gen_rtx (SUBREG, DFmode, operands[1], 0)));
-	  operands[1] = newreg;
+	  /* If operands[1] is a register, it may have double-precision data
+	     in it, so truncate it to single precision.  We need not do
+	     this for POWERPC.  */
+	  if (! TARGET_POWERPC && TARGET_HARD_FLOAT && GET_CODE (operands[1]) == REG)
+	    {
+	      rtx newreg = reload_in_progress ? operands[1] : gen_reg_rtx (SFmode);
+	      emit_insn (gen_truncdfsf2 (newreg,
+					 gen_rtx (SUBREG, DFmode, operands[1], 0)));
+	      operands[1] = newreg;
+	    }
+
+	  operands[1] = force_reg (SFmode, operands[1]);
 	}
 
-      operands[1] = force_reg (SFmode, operands[1]);
-    }
-
-  if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
-    {
-      if (GET_CODE (operands[1]) == MEM
+      if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
+	{
+	  if (GET_CODE (operands[1]) == MEM
 #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
-	  || GET_CODE (operands[1]) == CONST_DOUBLE
+	      || GET_CODE (operands[1]) == CONST_DOUBLE
 #endif
-	  || (GET_CODE (operands[1]) == REG
-	      && (REGNO (operands[1]) < 32
-		  || (reload_in_progress
-		      && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))))
-	{
-	  emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
-			  operand_subword (operands[1], 0, 0, SFmode));
-	  DONE;
-	}
-      else
-	{
-	  rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
-
-	  emit_move_insn (stack_slot, operands[1]);
-	  emit_move_insn (operands[0], stack_slot);
-	  DONE;
+	      || (GET_CODE (operands[1]) == REG
+		  && (REGNO (operands[1]) < 32
+		      || (reload_in_progress
+			  && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))))
+	    {
+	      emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
+			      operand_subword (operands[1], 0, 0, SFmode));
+	      DONE;
+	    }
+	  else
+	    {
+	      rtx stack_slot = assign_stack_temp (SFmode, 4, 0);
+
+	      emit_move_insn (stack_slot, operands[1]);
+	      emit_move_insn (operands[0], stack_slot);
+	      DONE;
+	    }
 	}
     }