From: Kaj Tuomi <kaj.tuomi@siru.fi>
Date: Tue, 17 Oct 2017 06:58:01 +0000 (+0300)
Subject: Fix input vector for reduce cells. Infinite loop fixed.
X-Git-Tag: working-ls180~833^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e558b3284b346b76ac2c06a0f6d61c9d53cba70c;p=yosys.git

Fix input vector for reduce cells. Infinite loop fixed.
---

diff --git a/passes/opt/opt_reduce.cc b/passes/opt/opt_reduce.cc
index eb9d02ad5..8126f3c0d 100644
--- a/passes/opt/opt_reduce.cc
+++ b/passes/opt/opt_reduce.cc
@@ -44,6 +44,7 @@ struct OptReduceWorker
 		cells.erase(cell);
 
 		RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+		sig_a.sort_and_unify();
 		pool<RTLIL::SigBit> new_sig_a_bits;
 
 		for (auto &bit : sig_a.to_sigbit_set())
@@ -86,6 +87,7 @@ struct OptReduceWorker
 		}
 
 		RTLIL::SigSpec new_sig_a(new_sig_a_bits);
+		new_sig_a.sort_and_unify();
 
 		if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
 			log("    New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));