From: Andrew Waterman <waterman@cs.berkeley.edu>
Date: Thu, 26 Mar 2015 06:01:54 +0000 (-0700)
Subject: Update state.pc on every instruction
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e5675bfcb3a8a798628317d6dccfbc9bd1ea3ebf;p=riscv-isa-sim.git

Update state.pc on every instruction

This isn't a bug fix for Spike proper, but it makes it possible for
RoCC instructions to access the control thread's PC.
---

diff --git a/riscv/processor.cc b/riscv/processor.cc
index c2d5275..0ff5578 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -193,7 +193,7 @@ void processor_t::step(size_t n)
       {
         insn_fetch_t fetch = mmu->load_insn(pc);
         disasm(fetch.insn);
-        pc = execute_insn(this, pc, fetch);
+        state.pc = pc = execute_insn(this, pc, fetch);
       }
     }
     else while (instret < n)
@@ -204,7 +204,7 @@ void processor_t::step(size_t n)
       #define ICACHE_ACCESS(idx) { \
         insn_fetch_t fetch = ic_entry->data; \
         ic_entry++; \
-        pc = execute_insn(this, pc, fetch); \
+        state.pc = pc = execute_insn(this, pc, fetch); \
         instret++; \
         if (idx == mmu_t::ICACHE_ENTRIES-1) break; \
         if (unlikely(ic_entry->tag != pc)) break; \
@@ -217,11 +217,10 @@ void processor_t::step(size_t n)
   }
   catch(trap_t& t)
   {
-    pc = take_trap(t, pc);
+    state.pc = take_trap(t, pc);
   }
   catch(serialize_t& s) {}
 
-  state.pc = pc;
   update_timer(&state, instret);
 }