From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 20 Jul 2014 09:00:09 +0000 (+0200)
Subject: Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
X-Git-Tag: yosys-0.4~529
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e57db5e9b256d801c1d4337e44e1a7173a115d07;p=yosys.git

Added std::set<RTLIL::SigBit> to RTLIL::SigSpec conversion
---

diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index dea0e1050..748deae3e 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1451,10 +1451,17 @@ RTLIL::SigSpec::SigSpec(RTLIL::SigBit bit, int width)
 
 RTLIL::SigSpec::SigSpec(std::vector<RTLIL::SigBit> bits)
 {
-	chunks.reserve(bits.size());
+	this->width = 0;
 	for (auto &bit : bits)
-		chunks.push_back(bit);
-	this->width = bits.size();
+		append_bit(bit);
+	check();
+}
+
+RTLIL::SigSpec::SigSpec(std::set<RTLIL::SigBit> bits)
+{
+	this->width = 0;
+	for (auto &bit : bits)
+		append_bit(bit);
 	check();
 }
 
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 6290db21d..64136de04 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -505,6 +505,7 @@ struct RTLIL::SigSpec {
 	SigSpec(RTLIL::State bit, int width = 1);
 	SigSpec(RTLIL::SigBit bit, int width = 1);
 	SigSpec(std::vector<RTLIL::SigBit> bits);
+	SigSpec(std::set<RTLIL::SigBit> bits);
 	void expand();
 	void optimize();
 	RTLIL::SigSpec optimized() const;