From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jul 2019 16:22:57 +0000 (+0100)
Subject: set reset_less=True - the data is protected by muxid.  if muxid not set,
X-Git-Tag: ls180-24jan2020~886
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e5a3263e50faf38a91e248ba1dafe26b6ab0c9ee;p=ieee754fpu.git

set reset_less=True - the data is protected by muxid.  if muxid not set,
data is invalid.  therefore reset is pointless (and wastes gates)
---

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
index 3d58d0de..0ee39351 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/test_core.py
@@ -144,10 +144,10 @@ class DivPipeCoreTestPipeline(Elaboratable):
             for stage_index in range(core_config.num_calculate_stages)]
         self.final_stage = DivPipeCoreFinalStage(core_config)
         self.interstage_signals = [
-            DivPipeCoreInterstageData(core_config, reset_less=False)
+            DivPipeCoreInterstageData(core_config, reset_less=True)
             for i in range(core_config.num_calculate_stages + 1)]
-        self.i = DivPipeCoreInputData(core_config, reset_less=False)
-        self.o = DivPipeCoreOutputData(core_config, reset_less=False)
+        self.i = DivPipeCoreInputData(core_config, reset_less=True)
+        self.o = DivPipeCoreOutputData(core_config, reset_less=True)
 
     def elaborate(self, platform):
         m = Module()