From: Zhang, Jun <jun.zhang@intel.com>
Date: Mon, 22 May 2023 14:01:38 +0000 (+0800)
Subject: Support Intel FRED LKGS
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e5a497fe38e0ab19e16bdd9e4b4ed5e4d0056478;p=binutils-gdb.git

Support Intel FRED LKGS

gas/ChangeLog:

        * NEWS: Support Intel FRED LKGS.
        * config/tc-i386.c: Add fred lkgs
        * doc/c-i386.texi: Document .fred, .lkgs.
        * testsuite/gas/i386/i386.exp: Add FRED LKGS tests
        * testsuite/gas/i386/x86-64-fred-intel.d: Ditto.
        * testsuite/gas/i386/x86-64-fred.d: Ditto.
        * testsuite/gas/i386/x86-64-fred.s: Ditto.
        * testsuite/gas/i386/x86-64-lkgs-intel.d: Ditto.
        * testsuite/gas/i386/x86-64-lkgs-inval.l: Ditto.
        * testsuite/gas/i386/x86-64-lkgs-inval.s: Ditto.
        * testsuite/gas/i386/x86-64-lkgs.d: Ditto.
        * testsuite/gas/i386/x86-64-lkgs.s: Ditto.

opcodes/ChangeLog:

        * i386-dis.c: New entry for fred, lkgs.
        * i386-gen.c: Add CPU_FRED CPU_LKGS.
        * i386-init.h : Regenerated.
        * i386-mnem.h : Regenerated.
        * i386-opc.h: Add fred, lkgs.
        * i386-opc.tbl: Add FRED, LKGS instructions.
        * i386-tbl.h: Regenerated.
---

diff --git a/gas/NEWS b/gas/NEWS
index 42a2005d7c9..ea172fe9cdb 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -1,5 +1,9 @@
 -*- text -*-
 
+* Add support for Intel FRED instructions.
+
+* Add support for Intel LKGS instructions.
+
 * Add support for Intel AMX-COMPLEX instructions.
 
 * Add SME2 support to the AArch64 port.
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index ca3626e3069..1002c5f564c 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1149,6 +1149,8 @@ static const arch_entry cpu_arch[] =
   SUBARCH (avx_ne_convert, AVX_NE_CONVERT, ANY_AVX_NE_CONVERT, false),
   SUBARCH (rao_int, RAO_INT, RAO_INT, false),
   SUBARCH (rmpquery, RMPQUERY, ANY_RMPQUERY, false),
+  SUBARCH (fred, FRED, ANY_FRED, false),
+  SUBARCH (lkgs, LKGS, ANY_LKGS, false),
 };
 
 #undef SUBARCH
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 15d060b2a33..49b6e3b1abb 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -205,6 +205,8 @@ accept various extension mnemonics.  For example,
 @code{msrlist},
 @code{avx_ne_convert},
 @code{rao_int},
+@code{fred},
+@code{lkgs},
 @code{amx_int8},
 @code{amx_bf16},
 @code{amx_fp16},
@@ -1634,6 +1636,7 @@ supported on the CPU specified.  The choices for @var{cpu_type} are:
 @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
 @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
 @item @samp{.avx_ne_convert} @tab @samp{.rao_int}
+@item @samp{.fred} @tab @samp{.lkgs}
 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index dc29b5112ab..c098f2de533 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -1191,6 +1191,9 @@ if [gas_64_check] then {
     run_dump_test "x86-64-amx-complex-intel"
     run_dump_test "x86-64-amx-complex-bad"
     run_list_test "x86-64-amx-complex-inval"
+    run_dump_test "x86-64-fred"
+    run_dump_test "x86-64-lkgs"
+    run_list_test "x86-64-lkgs-inval"
     run_dump_test "x86-64-clzero"
     run_dump_test "x86-64-mwaitx-bdver4"
     run_list_test "x86-64-mwaitx-reg"
diff --git a/gas/testsuite/gas/i386/x86-64-fred-intel.d b/gas/testsuite/gas/i386/x86-64-fred-intel.d
new file mode 100644
index 00000000000..aef98af2d81
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-fred-intel.d
@@ -0,0 +1,15 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 FRED insns (Intel disassembly)
+#source: x86-64-fred.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets
+\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu
+\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets
+\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-fred.d b/gas/testsuite/gas/i386/x86-64-fred.d
new file mode 100644
index 00000000000..01990f1cec8
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-fred.d
@@ -0,0 +1,15 @@
+#as:
+#objdump: -dw
+#name: x86_64 FRED insns
+#source: x86-64-fred.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets
+\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu
+\s*[a-f0-9]+:\s*f2 0f 01 ca\s+erets
+\s*[a-f0-9]+:\s*f3 0f 01 ca\s+eretu
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-fred.s b/gas/testsuite/gas/i386/x86-64-fred.s
new file mode 100644
index 00000000000..0e5d3d3d469
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-fred.s
@@ -0,0 +1,11 @@
+# Check 64bit FRED instructions
+
+	.allow_index_reg
+	.text
+_start:
+	erets		 #FRED
+	eretu		 #FRED
+
+.intel_syntax noprefix
+	erets		 #FRED
+	eretu		 #FRED
diff --git a/gas/testsuite/gas/i386/x86-64-lkgs-intel.d b/gas/testsuite/gas/i386/x86-64-lkgs-intel.d
new file mode 100644
index 00000000000..0f4a6fba6d3
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-lkgs-intel.d
@@ -0,0 +1,25 @@
+#as:
+#objdump: -dw -Mintel
+#name: x86_64 LKGS insns (Intel disassembly)
+#source: x86-64-lkgs.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs   r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs   r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs   r12w
+\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs   WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs   WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs   WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs   WORD PTR \[rdx-0x100\]
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs   r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs   r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs   r12w
+\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs   WORD PTR \[rbp\+r14\*8\+0x10000000\]
+\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs   WORD PTR \[r9\]
+\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs   WORD PTR \[rcx\+0xfe\]
+\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs   WORD PTR \[rdx-0x100\]
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-lkgs-inval.l b/gas/testsuite/gas/i386/x86-64-lkgs-inval.l
new file mode 100644
index 00000000000..77ee7d7c8b9
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-lkgs-inval.l
@@ -0,0 +1,9 @@
+.* Assembler messages:
+.*:5: Error: invalid instruction suffix for `lkgs'
+.*:6: Error: invalid instruction suffix for `lkgs'
+.*:7: Error: invalid instruction suffix for `lkgs'
+.*:8: Error: invalid instruction suffix for `lkgs'
+.*:11: Error: invalid instruction suffix for `lkgs'
+.*:12: Error: invalid instruction suffix for `lkgs'
+.*:13: Error: invalid instruction suffix for `lkgs'
+.*:14: Error: invalid instruction suffix for `lkgs'
diff --git a/gas/testsuite/gas/i386/x86-64-lkgs-inval.s b/gas/testsuite/gas/i386/x86-64-lkgs-inval.s
new file mode 100644
index 00000000000..1dbce14bae4
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-lkgs-inval.s
@@ -0,0 +1,14 @@
+# Check illegal 64bit suffer usage in LKGS instructions
+
+    .text
+_start:
+    lkgsb    %r12     #LKGS
+    lkgss    %r12     #LKGS
+    lkgsb    (%r9)    #LKGS
+    lkgss    (%r9)    #LKGS
+
+    .intel_syntax noprefix
+    lkgsb    %r12     #LKGS
+    lkgsb    BYTE PTR [r9]    #LKGS
+    lkgsd    DWORD PTR [r9]    #LKGS
+    lkgsq    QWORD PTR [r9]    #LKGS
diff --git a/gas/testsuite/gas/i386/x86-64-lkgs.d b/gas/testsuite/gas/i386/x86-64-lkgs.d
new file mode 100644
index 00000000000..207143da574
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-lkgs.d
@@ -0,0 +1,25 @@
+#as:
+#objdump: -dw
+#name: x86_64 LKGS insns
+#source: x86-64-lkgs.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs   %r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs   %r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs   %r12w
+\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs   0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs   \(%r9\)
+\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs   0xfe\(%rcx\)
+\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs   -0x100\(%rdx\)
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs   %r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs   %r12w
+\s*[a-f0-9]+:\s*f2 41 0f 00 f4\s+lkgs   %r12w
+\s*[a-f0-9]+:\s*f2 42 0f 00 b4 f5 00 00 00 10\s+lkgs   0x10000000\(%rbp,%r14,8\)
+\s*[a-f0-9]+:\s*f2 41 0f 00 31\s+lkgs   \(%r9\)
+\s*[a-f0-9]+:\s*f2 0f 00 b1 fe 00 00 00\s+lkgs   0xfe\(%rcx\)
+\s*[a-f0-9]+:\s*f2 0f 00 b2 00 ff ff ff\s+lkgs   -0x100\(%rdx\)
+#pass
diff --git a/gas/testsuite/gas/i386/x86-64-lkgs.s b/gas/testsuite/gas/i386/x86-64-lkgs.s
new file mode 100644
index 00000000000..546bbcc580a
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-lkgs.s
@@ -0,0 +1,21 @@
+# Check 64bit LKGS instructions
+
+	.allow_index_reg
+	.text
+_start:
+	lkgs	%r12	 #LKGS
+	lkgs    %r12w    #LKGS
+	lkgsw   %r12w    #LKGS
+	lkgs	0x10000000(%rbp, %r14, 8)	 #LKGS
+	lkgs	(%r9)	 #LKGS
+	lkgs	254(%rcx)	 #LKGS Disp32(fe000000)
+	lkgs	-256(%rdx)	 #LKGS Disp32(00ffffff)
+
+.intel_syntax noprefix
+	lkgs	r12	 #LKGS
+	lkgs	r12w	 #LKGS
+	lkgsw	r12w	 #LKGS
+	lkgs	WORD PTR [rbp+r14*8+0x10000000]	 #LKGS
+	lkgs	WORD PTR [r9]	 #LKGS
+	lkgs	WORD PTR [rcx+254]	 #LKGS Disp32(fe000000)
+	lkgs	WORD PTR [rdx-256]	 #LKGS Disp32(00ffffff)
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 23e8b095e49..07fcf3269f9 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -1016,7 +1016,9 @@ enum
 enum
 {
   PREFIX_90 = 0,
+  PREFIX_0F00_REG_6_X86_64,
   PREFIX_0F01_REG_0_MOD_3_RM_6,
+  PREFIX_0F01_REG_1_RM_2,
   PREFIX_0F01_REG_1_RM_4,
   PREFIX_0F01_REG_1_RM_5,
   PREFIX_0F01_REG_1_RM_6,
@@ -1301,10 +1303,13 @@ enum
   X86_64_E8,
   X86_64_E9,
   X86_64_EA,
+  X86_64_0F00_REG_6,
   X86_64_0F01_REG_0,
   X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
   X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
   X86_64_0F01_REG_1,
+  X86_64_0F01_REG_1_RM_2_PREFIX_1,
+  X86_64_0F01_REG_1_RM_2_PREFIX_3,
   X86_64_0F01_REG_1_RM_5_PREFIX_2,
   X86_64_0F01_REG_1_RM_6_PREFIX_2,
   X86_64_0F01_REG_1_RM_7_PREFIX_2,
@@ -2746,7 +2751,7 @@ static const struct dis386 reg_table[][8] = {
     { "ltr",	{ Ew }, 0 },
     { "verr",	{ Ew }, 0 },
     { "verw",	{ Ew }, 0 },
-    { Bad_Opcode },
+    { X86_64_TABLE (X86_64_0F00_REG_6) },
     { Bad_Opcode },
   },
   /* REG_0F01 */
@@ -2987,6 +2992,14 @@ static const struct dis386 prefix_table[][4] = {
     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
   },
 
+  /* PREFIX_0F00_REG_6_X86_64 */
+  {
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { Bad_Opcode },
+    { "lkgs",  { Ew }, 0 },
+  },
+
   /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
   {
     { "wrmsrns",        { Skip_MODRM }, 0 },
@@ -2995,6 +3008,14 @@ static const struct dis386 prefix_table[][4] = {
     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
   },
 
+  /* PREFIX_0F01_REG_1_RM_2 */
+  {
+    { "clac",		{ Skip_MODRM }, 0 },
+    { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) },
+    { Bad_Opcode },
+    { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)},
+  },
+
   /* PREFIX_0F01_REG_1_RM_4 */
   {
     { Bad_Opcode },
@@ -4362,6 +4383,12 @@ static const struct dis386 x86_64_table[][2] = {
     { "{l|}jmp{P|}", { Ap }, 0 },
   },
 
+  /* X86_64_0F00_REG_6 */
+  {
+    { Bad_Opcode },
+    { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
+  },
+
   /* X86_64_0F01_REG_0 */
   {
     { "sgdt{Q|Q}", { M }, 0 },
@@ -4386,6 +4413,18 @@ static const struct dis386 x86_64_table[][2] = {
     { "sidt", { M }, 0 },
   },
 
+  /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
+  {
+    { Bad_Opcode },
+    { "eretu",		{ Skip_MODRM }, 0 },
+  },
+
+  /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
+  {
+    { Bad_Opcode },
+    { "erets",		{ Skip_MODRM }, 0 },
+  },
+
   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
   {
     { Bad_Opcode },
@@ -8693,7 +8732,7 @@ static const struct dis386 rm_table[][8] = {
     /* RM_0F01_REG_1 */
     { "monitor",	{ { OP_Monitor, 0 } }, 0 },
     { "mwait",		{ { OP_Mwait, 0 } }, 0 },
-    { "clac",		{ Skip_MODRM }, 0 },
+    { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
     { "stac",		{ Skip_MODRM }, 0 },
     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index c2ac3c6832d..1db555d8615 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -164,6 +164,8 @@ static const dependency isa_dependencies[] =
     "AVX2" },
   { "AVX_NE_CONVERT",
     "AVX2" },
+  { "FRED",
+    "LKGS" },
   { "AVX512F",
     "AVX2" },
   { "AVX512CD",
@@ -362,6 +364,8 @@ static bitfield cpu_flags[] =
   BITFIELD (MSRLIST),
   BITFIELD (AVX_NE_CONVERT),
   BITFIELD (RAO_INT),
+  BITFIELD (FRED),
+  BITFIELD (LKGS),
   BITFIELD (MWAITX),
   BITFIELD (CLZERO),
   BITFIELD (OSPKE),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index b17e8341aa2..d65392aca8d 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -229,6 +229,10 @@ enum
   CpuAVX_NE_CONVERT,
   /* Intel RAO INT Instructions support required.  */
   CpuRAO_INT,
+  /* fred instruction required */
+  CpuFRED,
+  /* lkgs instruction required */
+  CpuLKGS,
   /* mwaitx instruction required */
   CpuMWAITX,
   /* Clzero instruction required */
@@ -424,6 +428,8 @@ typedef union i386_cpu_flags
       unsigned int cpumsrlist:1;
       unsigned int cpuavx_ne_convert:1;
       unsigned int cpurao_int:1;
+      unsigned int cpufred:1;
+      unsigned int cpulkgs:1;
       unsigned int cpumwaitx:1;
       unsigned int cpuclzero:1;
       unsigned int cpuospke:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 15d48eeb4c7..c1d323310e5 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3351,3 +3351,17 @@ aor, 0xf20f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64
 axor, 0xf30f38fc, RAO_INT, Modrm|IgnoreSize|CheckOperandSize|NoSuf, { Reg32|Reg64, Dword|Qword|Unspecified|BaseIndex }
 
 // RAO-INT instructions end.
+
+// LKGS instruction.
+
+lkgs, 0xf20f00/6, LKGS|x64, Modrm|IgnoreSize|No_bSuf|No_sSuf|NoRex64, { Reg16|Reg32|Reg64 }
+lkgs, 0xf20f00/6, LKGS|x64, Modrm|IgnoreSize|No_bSuf|No_lSuf|No_sSuf|No_qSuf, { Word|Unspecified|BaseIndex }
+
+// LKGS instruction end.
+
+// FRED instructions.
+
+erets, 0xf20f01ca, FRED|x64, NoSuf, {}
+eretu, 0xf30f01ca, FRED|x64, NoSuf, {}
+
+// FRED instructions end.