From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 12 Aug 2014 13:39:48 +0000 (+0200)
Subject: Fixed SigBit(RTLIL::Wire *wire) constructor
X-Git-Tag: yosys-0.4~279
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e5ac8fdf2bf9d4bed41daf420aa8a94018c0ded4;p=yosys.git

Fixed SigBit(RTLIL::Wire *wire) constructor
---

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 8ec599417..1e967f26c 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -852,7 +852,7 @@ struct RTLIL::SigBit
 
 	SigBit() : wire(NULL), data(RTLIL::State::S0) { }
 	SigBit(RTLIL::State bit) : wire(NULL), data(bit) { }
-	SigBit(RTLIL::Wire *wire) : wire(wire), data(RTLIL::State::S0) { log_assert(wire && wire->width == 1); }
+	SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); }
 	SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire); }
 	SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data.bits[0]; }
 	SigBit(const RTLIL::SigChunk &chunk, int index) : wire(chunk.wire) { if (wire) offset = chunk.offset + index; else data = chunk.data.bits[index]; }