From: lkcl <lkcl@web>
Date: Mon, 6 Sep 2021 15:49:13 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~206
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e5afd555cbe301d377475bc900de1416141231a0;p=libreriscv.git

---

diff --git a/openpower/sv/ldst.mdwn b/openpower/sv/ldst.mdwn
index 12115f6c5..b2a500a02 100644
--- a/openpower/sv/ldst.mdwn
+++ b/openpower/sv/ldst.mdwn
@@ -45,7 +45,7 @@ a number of different modes:
 * Structure Packing (covered in SV by [[sv/remap]]).
 
 Also included in SVP64 LD/ST is both signed and unsigned Saturation,
-as well as Eement-width overrides and Twin-Predication.
+as well as Element-width overrides and Twin-Predication.
 
 # Vectorisation of Scalar Power ISA v3.0B