From: Cesar Strauss <cestrauss@gmail.com>
Date: Mon, 22 Mar 2021 11:46:22 +0000 (-0300)
Subject: Add test cases for integer VCOMPRESS and VEXPAND
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e5b6dadea886c72b4e37395728e0305d6b9369cd;p=soc.git

Add test cases for integer VCOMPRESS and VEXPAND

In these cases, either srcmask or destmask is "always", so the
corresponding mask should be all ones, instead of being fetched from the
register file.
---

diff --git a/src/soc/fu/alu/test/svp64_cases.py b/src/soc/fu/alu/test/svp64_cases.py
index 3b42ef4a..d7341224 100644
--- a/src/soc/fu/alu/test/svp64_cases.py
+++ b/src/soc/fu/alu/test/svp64_cases.py
@@ -245,3 +245,69 @@ class SVP64ALUTestCase(TestAccumulatorBase):
 
         self.add_case(Program(lst, bigendian), initial_regs,
                       initial_svstate=svstate)
+
+    @skip_case("Predication not implemented yet")
+    def case_10_intpred_vcompress(self):
+        #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
+        #   src r3=0b101                     Y  N  Y
+        #                                    |     |
+        #                            +-------+     |
+        #                            | +-----------+
+        #                            | |
+        #   dest always              Y Y Y
+
+        # expected results:
+        # r5 = 0xffff_ffff_ffff_ff90 (from r9)
+        # r6 = 0xffff_ffff_ffff_ff92 (from r11)
+        # r7 = 0x0 (VL loop runs out before we can use it)
+        isa = SVP64Asm(['sv.extsb/sm=r3 5.v, 9.v'])
+        lst = list(isa)
+        print("listing", lst)
+
+        # initial values in GPR regfile
+        initial_regs = [0] * 32
+        initial_regs[3] = 0b101  # predicate mask
+        initial_regs[9] = 0x90   # source r3 is 0b101 so this will be used
+        initial_regs[10] = 0x91  # this gets skipped
+        initial_regs[11] = 0x92  # source r3 is 0b101 so this will be used
+        # SVSTATE (in this case, VL=3)
+        svstate = SVP64State()
+        svstate.vl[0:7] = 3  # VL
+        svstate.maxvl[0:7] = 3  # MAXVL
+        print("SVSTATE", bin(svstate.spr.asint()))
+
+        self.add_case(Program(lst, bigendian), initial_regs,
+                      initial_svstate=svstate)
+
+    @skip_case("Predication not implemented yet")
+    def case_11_intpred_vexpand(self):
+        #   reg num        0 1 2 3 4 5 6 7 8 9 10 11
+        #   src always                       Y  Y  Y
+        #                                    |  |
+        #                            +-------+  |
+        #                            |   +------+
+        #                            |   |
+        #   dest r3=0b101            Y N Y
+
+        # expected results:
+        # r5 = 0xffff_ffff_ffff_ff90 1st bit of r3 is 1
+        # r6 = 0x0                   skip
+        # r7 = 0xffff_ffff_ffff_ff91 3nd bit of r3 is 1
+        isa = SVP64Asm(['sv.extsb/m=r3 5.v, 9.v'])
+        lst = list(isa)
+        print("listing", lst)
+
+        # initial values in GPR regfile
+        initial_regs = [0] * 32
+        initial_regs[3] = 0b101  # predicate mask
+        initial_regs[9] = 0x90   # source is "always", so this will be used
+        initial_regs[10] = 0x91  # likewise
+        initial_regs[11] = 0x92  # the VL loop runs out before we can use it
+        # SVSTATE (in this case, VL=3)
+        svstate = SVP64State()
+        svstate.vl[0:7] = 3  # VL
+        svstate.maxvl[0:7] = 3  # MAXVL
+        print("SVSTATE", bin(svstate.spr.asint()))
+
+        self.add_case(Program(lst, bigendian), initial_regs,
+                      initial_svstate=svstate)