From: Lionel Landwerlin Date: Thu, 3 Jan 2019 16:13:14 +0000 (+0000) Subject: i965: limit VF caching workaround to gen8/9/10 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e5ed217545198088673440f5e2e5ee435d8072fd;p=mesa.git i965: limit VF caching workaround to gen8/9/10 Documentation of the 3DSTATE_VERTEX_BUFFERS packet says this is only needed before ICL. Signed-off-by: Lionel Landwerlin Reviewed-by: Jason Ekstrand Reviewed-by: Kenneth Graunke --- diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c b/src/mesa/drivers/dri/i965/genX_blorp_exec.c index a62b88e166c..bb84317e1a0 100644 --- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c +++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c @@ -197,7 +197,7 @@ blorp_vf_invalidate_for_vb_48b_transitions(struct blorp_batch *batch, const struct blorp_address *addrs, unsigned num_vbs) { -#if GEN_GEN >= 8 +#if GEN_GEN >= 8 && GEN_GEN < 11 struct brw_context *brw = batch->driver_batch; bool need_invalidate = false; diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index 8c38d5f4e82..7f7406a68de 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -530,11 +530,13 @@ pinned_bo_high_bits(struct brw_bo *bo) * In the relocation world, we have no idea what the addresses will be, so * we can't apply this workaround. Instead, we tell the kernel to move it * to the low 4GB regardless. + * + * This HW issue is gone on Gen11+. */ static void vf_invalidate_for_vb_48bit_transitions(struct brw_context *brw) { -#if GEN_GEN >= 8 +#if GEN_GEN >= 8 && GEN_GEN < 11 bool need_invalidate = false; unsigned i;