From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 29 Jul 2014 18:14:25 +0000 (+0200)
Subject: Fixed Verilog pre-processor for files with no trailing newline
X-Git-Tag: yosys-0.4~367
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e605af8a4937533b35068071e14f5bd92c2e5b4f;p=yosys.git

Fixed Verilog pre-processor for files with no trailing newline
---

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 67b2ffa7c..9ff68822e 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -198,7 +198,7 @@ static void input_file(FILE *f, std::string filename)
 		buffer[rc] = 0;
 		input_buffer.insert(it, buffer);
 	}
-	input_buffer.insert(it, "`file_pop\n");
+	input_buffer.insert(it, "\n`file_pop\n");
 }
 
 std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::map<std::string, std::string> pre_defines_map, const std::list<std::string> include_dirs)