From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sun, 11 Aug 2019 08:46:48 +0000 (+0200)
Subject: Fixed data width
X-Git-Tag: working-ls180~1116^2~4
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e609537e386535047f045bf0b8df7ebc5f23c469;p=yosys.git

Fixed data width
---

diff --git a/techlibs/efinix/brams_map.v b/techlibs/efinix/brams_map.v
index 9ef01d026..3236f39a5 100644
--- a/techlibs/efinix/brams_map.v
+++ b/techlibs/efinix/brams_map.v
@@ -22,8 +22,8 @@ module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
 	localparam WRITEMODE_A = TRANSP2 ? "WRITE_FIRST" : "READ_FIRST";
 
 	EFX_RAM_5K #(
-   		.READ_WIDTH(20),
-   		.WRITE_WIDTH(20),
+   		.READ_WIDTH(CFG_DBITS),
+   		.WRITE_WIDTH(CFG_DBITS),
    		.OUTPUT_REG(1'b0),
    		.RCLK_POLARITY(1'b1),
    		.RE_POLARITY(1'b1),