From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 02:00:36 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into xaig
X-Git-Tag: working-ls180~1237^2~79
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e612dade12b30bdee15b7dd2535af51e5ec1614d;p=yosys.git

Merge remote-tracking branch 'origin/master' into xaig
---

e612dade12b30bdee15b7dd2535af51e5ec1614d
diff --cc CHANGELOG
index 44e32c6a8,4c38f6e6e..fd72d5702
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -17,11 -17,8 +17,11 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "rename -src"
      - Added "equiv_opt" pass
      - Added "read_aiger" frontend
 +    - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
 +    - Added "synth_xilinx -abc9" (experimental)
 +    - Added "synth_ice40 -abc9" (experimental)
 +    - Added "synth -abc9" (experimental)
-     - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
+     - Extended "muxcover -mux{4,8,16}=<cost>"
 -    - "synth_xilinx" to now infer hard shift registers, using new "shregmap -tech xilinx"
  
  
  Yosys 0.7 .. Yosys 0.8