From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Wed, 28 Jun 2017 16:08:37 +0000 (+0200)
Subject: board/targets/sim: add identifier
X-Git-Tag: 24jan2021_ls180~1828
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e61d9eabc6acf093430306a557df286c84a6a12a;p=litex.git

board/targets/sim: add identifier
---

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index 50cac545..1624441f 100755
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -28,6 +28,7 @@ class BaseSoC(SoCSDRAM):
         SoCSDRAM.__init__(self, platform,
             clk_freq=int((1/(platform.default_clk_period))*1000000000),
             integrated_rom_size=0x8000,
+            ident="LiteX simulation example design",
             with_uart=False,
             **kwargs)
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))