From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Mon, 14 Aug 2017 22:32:07 +0000 (-0700)
Subject: Fixed bug causing GP_SPI model to not synthesize
X-Git-Tag: yosys-0.8~332^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e62362225c8a53de1007f6ecc69b58b9bf1fdad9;p=yosys.git

Fixed bug causing GP_SPI model to not synthesize
---

diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v
index 2d7bed5cd..15bbba723 100644
--- a/techlibs/greenpak4/cells_sim.v
+++ b/techlibs/greenpak4/cells_sim.v
@@ -113,8 +113,8 @@ module GP_SPI(
 	output reg[7:0] RXD_LOW,
 	output reg INT);
 
-	initial DOUT_HIGH = 0;
-	initial DOUT_LOW = 0;
+	initial RXD_HIGH = 0;
+	initial RXD_LOW = 0;
 	initial INT = 0;
 
 	parameter DATA_WIDTH = 8;		//byte or word width