From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 00:03:05 +0000 (-0700)
Subject: Actually, there might not be any harm in updating sigmap...
X-Git-Tag: yosys-0.9~53^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e63324f5ef2ebb14fa0cc88544f577406f95b223;p=yosys.git

Actually, there might not be any harm in updating sigmap...
---

diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index 8881ba468..d9d1e257b 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -304,11 +304,9 @@ struct ShregmapWorker
 						// so that it can be identified as another chain
 						// (omitting this common flop)
 						// Link: https://github.com/YosysHQ/yosys/pull/1085
-						// NB: This relies on us not updating sigmap with this
-						//     alias otherwise it would think they are the same
-						//     wire
 						Wire *wire = module->addWire(NEW_ID);
 						module->connect(wire, d_bit);
+						sigmap.add(wire, d_bit);
 						sigbit_chain_next.insert(std::make_pair(wire, cell));
 					}