From: Yunsup Lee <yunsup@cs.berkeley.edu>
Date: Sat, 19 Oct 2013 02:22:08 +0000 (-0700)
Subject: clean up SR_EA, the enable accelerator bit in status reg
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e638446bd99d5051b1d5a45dd38dab654b153f6a;p=riscv-isa-sim.git

clean up SR_EA, the enable accelerator bit in status reg
---

diff --git a/riscv/pcr.h b/riscv/pcr.h
index 75a349f..b90884b 100644
--- a/riscv/pcr.h
+++ b/riscv/pcr.h
@@ -11,10 +11,10 @@
 #define SR_U64   0x00000020
 #define SR_S64   0x00000040
 #define SR_VM    0x00000080
-#define SR_EV    0x00000100
+#define SR_EA    0x00000100
 #define SR_IM    0x00FF0000
 #define SR_IP    0xFF000000
-#define SR_ZERO  ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EV|SR_IM|SR_IP)
+#define SR_ZERO  ~(SR_S|SR_PS|SR_EI|SR_PEI|SR_EF|SR_U64|SR_S64|SR_VM|SR_EA|SR_IM|SR_IP)
 #define SR_IM_SHIFT 16
 #define SR_IP_SHIFT 24
 
diff --git a/riscv/processor.cc b/riscv/processor.cc
index ac5c1f7..3fe0d99 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -210,9 +210,8 @@ reg_t processor_t::set_pcr(int which, reg_t val)
 #ifndef RISCV_ENABLE_FPU
       state.sr &= ~SR_EF;
 #endif
-#ifndef RISCV_ENABLE_VEC
-      state.sr &= ~SR_EV;
-#endif
+      if (!ext)
+        state.sr &= ~SR_EA;
       state.sr &= ~SR_ZERO;
       mmu->flush_tlb();
       break;