From: Luke Kenneth Casson Leighton Date: Fri, 24 May 2019 07:12:03 +0000 (+0100) Subject: add priority picker docstring X-Git-Tag: div_pipeline~1966 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e63f2d5ed2f45b4d92c9203c171f8568461dec0a;p=soc.git add priority picker docstring --- diff --git a/src/experiment/compalu.py b/src/experiment/compalu.py index bcd71b0c..1df0cc25 100644 --- a/src/experiment/compalu.py +++ b/src/experiment/compalu.py @@ -18,7 +18,7 @@ from nmutil.latch import SRLatch, latchregister The src1 and src2 registers and the operand can be latched in at this point - * Read request is set, which is ackowledged through the Scoreboard + * Read request is set, which is acknowledged through the Scoreboard to the priority picker, which generates (one and only one) Go_Read at a time. One of those will (eventually) be this Computation Unit. diff --git a/src/scoreboard/group_picker.py b/src/scoreboard/group_picker.py index f02f8863..133b3720 100644 --- a/src/scoreboard/group_picker.py +++ b/src/scoreboard/group_picker.py @@ -2,6 +2,49 @@ from nmigen.compat.sim import run_simulation from nmigen.cli import verilog, rtlil from nmigen import Module, Signal, Cat, Elaboratable +""" Group Picker: to select an instruction that is permitted to read (or write) + based on the Function Unit expressing a *desire* to read (or write). + + The job of the Group Picker is extremely simple yet extremely important. + It sits in front of a register file port (read or write) and stops it from + being corrupted. It's a "port contention selector", basically. + + The way it works is: + + * Function Units need to read from (or write to) the register file, + in order to get (or store) their operands, so they each have a signal, + readable (or writable), which "expresses" this need. This is an + *unary* encoding. + + * The Function Units also have a signal which indicates that they + are requesting "release" of the register file port (this because + in the scoreboard, readable/writable can be permanently HI even + if the FU is idle, whereas the "release" signal is very specifically + only HI if the read (or write) latch is still active) + + * The Group Picker takes this unary encoding of the desire to read + (or write) and, on a priority basis, activates one *and only* one + of those signals, again as an unary output. + + * Due to the way that the Computation Unit works, that signal (Go_Read + or Go_Write) will fire for one (and only one) cycle, and can be used + to enable the register file port read (or write) lines. The Go_Read/Wr + signal basically loops back to the Computation Unit and resets the + "desire-to-read/write-expressing" latch. + + In theory (and in practice!) the following is possible: + + * Separate src1 and src2 Group Pickers. This would allow instructions + with only one operand to read to not block up other instructions, + and it would also allow 3-operand instructions to be interleaved + with 1 and 2 operand instructions. + + * *Multiple* Group Pickers (multi-issue). This would require + a corresponding increase in the number of register file ports, + either 4R2W (or more) or by "striping" the register file into + split banks (a strategy best deployed on Vector Processors) + +""" class PriorityPicker(Elaboratable): """ implements a priority-picker. input: N bits, output: N bits