From: lkcl <lkcl@web>
Date: Wed, 15 Sep 2021 07:16:28 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~133
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e64539b860f0578eed6bed4f86daf71f7864a27f;p=libreriscv.git

---

diff --git a/openpower/sv/cr_ops.mdwn b/openpower/sv/cr_ops.mdwn
index c04868f93..e2b202ea1 100644
--- a/openpower/sv/cr_ops.mdwn
+++ b/openpower/sv/cr_ops.mdwn
@@ -29,11 +29,16 @@ are firmly out of scope for
 this section.
 
 * Examples of v3.0B instructions to which this section does
-  apply is `mfcr` (3 bit operands) and `crnor` (5 bit operands).
+  apply is `mfcr` (3 bit operands) and `crnor` and `cmpi`
+  (5 bit operands).
 * Examples to which this section does **not** apply include
   `fadds.` and `subf.` which both produce arithmetic results
   (and a CR Field co-result).
 
+The CR Mode Format still applies to `sv.cmpi` because despite
+taking a GPR as input, the output from the Base Scalar v3.0B `cmpi`
+instruction is purely to a Condition Register Field.
+
 Other modes are still applicable and include:
 
 * **Data-dependent fail-first**.