From: lkcl <lkcl@web>
Date: Sat, 7 May 2022 00:38:48 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2348
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e64b482979edcf0812ff1f6404867be83de30e80;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index af7048095..4633c74e5 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -29,7 +29,8 @@ Therefore it begs the question, why on earth would anyone consider
 this task, and what, in Computer Science, actually needs solving?
 
 First hints are that whilst memory bitcells have not increased in speed
-since the 90s (around 150 mhz), increasing the datapath widths has allowed
+since the 90s (around 150 mhz), increasing the bank width and
+datapath widths and speeds to the same has allowed
 significant apparent speed increases: 3200 mhz DDR4 and even faster DDR5,
 and other advanced Memory interfaces such as HBM, Gen-Z, and OpenCAPI,
 all make an effort (all simply increasing the parallel deployment of