From: Clifford Wolf <clifford@clifford.at>
Date: Fri, 29 Sep 2017 15:52:57 +0000 (+0200)
Subject: Fix synth_ice40 doc regarding -top default
X-Git-Tag: yosys-0.8~309
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e64b9d5a4d40ff5a86f35a17ac81786a647726d3;p=yosys.git

Fix synth_ice40 doc regarding -top default
---

diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc
index 2533d3af8..a49372c8a 100644
--- a/techlibs/ice40/synth_ice40.cc
+++ b/techlibs/ice40/synth_ice40.cc
@@ -38,7 +38,7 @@ struct SynthIce40Pass : public ScriptPass
 		log("This command runs synthesis for iCE40 FPGAs.\n");
 		log("\n");
 		log("    -top <module>\n");
-		log("        use the specified module as top module (default='top')\n");
+		log("        use the specified module as top module\n");
 		log("\n");
 		log("    -blif <file>\n");
 		log("        write the design to the specified BLIF file. writing of an output file\n");