From: Gabe Black <gabe.black@gmail.com>
Date: Fri, 29 Jan 2021 01:18:26 +0000 (-0800)
Subject: arch-arm,cpu: Introduce a getEMI virtual method on StaticInst.
X-Git-Tag: develop-gem5-snapshot~161
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e656730f356edf86879abc522862c267c90ab3de;p=gem5.git

arch-arm,cpu: Introduce a getEMI virtual method on StaticInst.

This takes the place of direct access to the machInst field as used in
the MinorCPU model which makes the incorrect assumption that it can
arbitrarily treat the ExtMachInst as an integer, and that masking in a
certain way can meaningfully classify what the instruction will do.

Because that assumption is not correct in general, that had been
ifdef-ed out in most ISAs except ARM, and for the other ISAs the value
was simply set to zero.

Change-Id: I8ac05e65475edc3ccc044afdff09490e2c05ba07
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/40098
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index e101d93fa..908641c49 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -197,6 +197,8 @@ class ArmStaticInst : public StaticInst
         pcState.advance();
     }
 
+    uint64_t getEMI() const override { return machInst; }
+
     std::string generateDisassembly(
             Addr pc, const Loader::SymbolTable *symtab) const override;
 
diff --git a/src/cpu/minor/func_unit.cc b/src/cpu/minor/func_unit.cc
index 58f3a1e72..8c5e3a6bb 100644
--- a/src/cpu/minor/func_unit.cc
+++ b/src/cpu/minor/func_unit.cc
@@ -171,13 +171,12 @@ FUPipeline::advance()
 MinorFUTiming *
 FUPipeline::findTiming(const StaticInstPtr &inst)
 {
-#if THE_ISA == ARM_ISA
-    /* This should work for any ISA with a POD mach_inst */
-    TheISA::ExtMachInst mach_inst = inst->machInst;
-#else
-    /* Just allow extra decode based on op classes */
-    uint64_t mach_inst = 0;
-#endif
+    /*
+     * This will only work on ISAs with an instruction format with a fixed size
+     * which can be categorized using bit masks. This is really only supported
+     * on ARM and is a bit of a hack.
+     */
+    uint64_t mach_inst = inst->getEMI();
 
     const std::vector<MinorFUTiming *> &timings =
         description.timings;
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index 09f171f5b..b2cd50851 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -258,6 +258,8 @@ class StaticInst : public RefCounted, public StaticInstFlags
     /// The binary machine instruction.
     const TheISA::ExtMachInst machInst;
 
+    virtual uint64_t getEMI() const { return 0; }
+
   protected:
 
     /**