From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Sat, 11 Jun 2011 23:13:59 +0000 (-0700)
Subject: [xcc] fix configure scripts
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e665e552b3944f4003f2cef76f650b38570cb854;p=riscv-isa-sim.git

[xcc] fix configure scripts
---

diff --git a/configure b/configure
index eda5f6c..cca7f14 100755
--- a/configure
+++ b/configure
@@ -1274,9 +1274,9 @@ Optional Features:
                           Enable all optional subprojects
   --disable-fpu           Disable floating-point
   --disable-64bit         Disable 64-bit mode
-  --disable-rvc           Disable instruction compression
+  --enable-rvc            Enable instruction compression
   --disable-vec           Disable vector processor
-  --disable-icsim         Enable instruction cache simulator
+  --enable-icsim          Enable instruction cache simulator
 
 Some influential environment variables:
   CC          C compiler command
@@ -4056,7 +4056,7 @@ if test "${enable_rvc+set}" = set; then :
   enableval=$enable_rvc;
 fi
 
-if test "x$enable_rvc" != "xno"; then :
+if test "x$enable_rvc" = "xyes"; then :
 
 
 $as_echo "#define RISCV_ENABLE_RVC /**/" >>confdefs.h
diff --git a/riscv/riscv.ac b/riscv/riscv.ac
index 897b21f..00358fd 100644
--- a/riscv/riscv.ac
+++ b/riscv/riscv.ac
@@ -8,8 +8,8 @@ AS_IF([test "x$enable_64bit" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_64BIT],,[Define if 64-bit mode is supported])
 ])
 
-AC_ARG_ENABLE([rvc], AS_HELP_STRING([--disable-rvc], [Disable instruction compression]))
-AS_IF([test "x$enable_rvc" != "xno"], [
+AC_ARG_ENABLE([rvc], AS_HELP_STRING([--enable-rvc], [Enable instruction compression]))
+AS_IF([test "x$enable_rvc" = "xyes"], [
   AC_DEFINE([RISCV_ENABLE_RVC],,[Define if instruction compression is supported])
 ])
 
@@ -18,7 +18,7 @@ AS_IF([test "x$enable_vec" != "xno"], [
   AC_DEFINE([RISCV_ENABLE_VEC],,[Define if vector processor is supported])
 ])
 
-AC_ARG_ENABLE([icsim], AS_HELP_STRING([--disable-icsim], [Enable instruction cache simulator]))
+AC_ARG_ENABLE([icsim], AS_HELP_STRING([--enable-icsim], [Enable instruction cache simulator]))
 AS_IF([test "x$enable_icsim" = "xyes"], [
   AC_DEFINE([RISCV_ENABLE_ICSIM],,[Define if instruction cache simulator is enabled])
 ])