From: Aldy Hernandez <aldyh@redhat.com>
Date: Wed, 11 Feb 2004 12:37:21 +0000 (+0000)
Subject: spe.md ("*movv2si_internal"): Check for register operand.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e66b2fcf9796f050419ab428b766540375c57f05;p=gcc.git

spe.md ("*movv2si_internal"): Check for register operand.

        * config/rs6000/spe.md ("*movv2si_internal"): Check for register
        operand.

From-SVN: r77651
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 383c3a5a076..5eb07365f70 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2004-02-10  Aldy Hernandez  <aldyh@redhat.com>
+                                                                                
+        * config/rs6000/spe.md ("*movv2si_internal"): Check for register
+        operand.
+
 2004-02-11  Thiemo Seufer  <seufer@csv.ica.uni-stuttgart.de>
 
 	* config/mips/mips.h (TARGET_OLDABI): Define. Use TARGET_NEWABI and
diff --git a/gcc/config/rs6000/spe.md b/gcc/config/rs6000/spe.md
index becdaa42bb2..d3ecbe018fd 100644
--- a/gcc/config/rs6000/spe.md
+++ b/gcc/config/rs6000/spe.md
@@ -2165,7 +2165,9 @@
 (define_insn "*movv2si_internal"
   [(set (match_operand:V2SI 0 "nonimmediate_operand" "=m,r,r,r")
 	(match_operand:V2SI 1 "input_operand" "r,m,r,W"))]
-  "TARGET_SPE"
+  "TARGET_SPE
+   && (gpc_reg_operand (operands[0], V2SImode)
+       || gpc_reg_operand (operands[1], V2SImode))"
   "*
 {
   switch (which_alternative)
@@ -2197,7 +2199,9 @@
 (define_insn "*movv1di_internal"
   [(set (match_operand:V1DI 0 "nonimmediate_operand" "=m,r,r,r")
 	(match_operand:V1DI 1 "input_operand" "r,m,r,W"))]
-  "TARGET_SPE"
+  "TARGET_SPE
+   && (gpc_reg_operand (operands[0], V1DImode)
+       || gpc_reg_operand (operands[1], V1DImode))"
   "@
    evstdd%X0 %1,%y0
    evldd%X1 %0,%y1
@@ -2215,7 +2219,9 @@
 (define_insn "*movv4hi_internal"
   [(set (match_operand:V4HI 0 "nonimmediate_operand" "=m,r,r")
 	(match_operand:V4HI 1 "input_operand" "r,m,r"))]
-  "TARGET_SPE"
+  "TARGET_SPE
+   && (gpc_reg_operand (operands[0], V4HImode)
+       || gpc_reg_operand (operands[1], V4HImode))"
   "@
    evstdd%X0 %1,%y0
    evldd%X1 %0,%y1
@@ -2231,7 +2237,9 @@
 (define_insn "*movv2sf_internal"
   [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,r,r,r")
 	(match_operand:V2SF 1 "input_operand" "r,m,r,W"))]
-  "TARGET_SPE"
+  "TARGET_SPE
+   && (gpc_reg_operand (operands[0], V2SFmode)
+       || gpc_reg_operand (operands[1], V2SFmode))"
   "@
    evstdd%X0 %1,%y0
    evldd%X1 %0,%y1
@@ -2240,6 +2248,8 @@
   [(set_attr "type" "vecload,vecstore,*,*")
    (set_attr "length" "*,*,*,*")])
 
+;; End of vector move instructions.
+
 (define_insn "spe_evmwhssfaa"
   [(set (match_operand:V2SI 0 "gpc_reg_operand" "=r")
         (unspec:V2SI [(match_operand:V2SI 1 "gpc_reg_operand" "r")