From: Florent Kermarrec Date: Fri, 9 Aug 2019 10:33:10 +0000 (+0200) Subject: cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus X-Git-Tag: 24jan2021_ls180~1055 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e670cb91767f564dffc38b40de53b8133a70f858;p=litex.git cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus --- diff --git a/litex/soc/cores/cpu/minerva/core.py b/litex/soc/cores/cpu/minerva/core.py index 73194546..05007cf5 100644 --- a/litex/soc/cores/cpu/minerva/core.py +++ b/litex/soc/cores/cpu/minerva/core.py @@ -22,7 +22,7 @@ class Minerva(Module): @property def gcc_triple(self): - return ("riscv64-unknown-elf", "riscv32-unknown-elf") + return ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed") @property def gcc_flags(self): diff --git a/litex/soc/cores/cpu/picorv32/core.py b/litex/soc/cores/cpu/picorv32/core.py index 40b9c5b6..7a3c5600 100644 --- a/litex/soc/cores/cpu/picorv32/core.py +++ b/litex/soc/cores/cpu/picorv32/core.py @@ -40,7 +40,7 @@ class PicoRV32(Module): @property def gcc_triple(self): - return ("riscv64-unknown-elf", "riscv32-unknown-elf") + return ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed") @property def gcc_flags(self): diff --git a/litex/soc/cores/cpu/vexriscv/core.py b/litex/soc/cores/cpu/vexriscv/core.py index 2111375b..6c6cc08b 100644 --- a/litex/soc/cores/cpu/vexriscv/core.py +++ b/litex/soc/cores/cpu/vexriscv/core.py @@ -84,7 +84,7 @@ class VexRiscv(Module, AutoCSR): @property def gcc_triple(self): - return ("riscv64-unknown-elf", "riscv32-unknown-elf") + return ("riscv64-unknown-elf", "riscv32-unknown-elf", "riscv-none-embed") @property def gcc_flags(self):