From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 24 Oct 2013 09:37:54 +0000 (+0200)
Subject: Fixed handling of boolean attributes (passes)
X-Git-Tag: yosys-0.2.0~449
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e679a5d04633e0c0626057ed2760ddb9595eea5d;p=yosys.git

Fixed handling of boolean attributes (passes)
---

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 87271bbf9..9fae954c1 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -368,7 +368,7 @@ struct RTLIL::CaseRule {
 
 struct RTLIL::SwitchRule {
 	RTLIL::SigSpec signal;
-	std::map<RTLIL::IdString, RTLIL::Const> attributes;
+	RTLIL_ATTRIBUTE_MEMBERS
 	std::vector<RTLIL::CaseRule*> cases;
 	~SwitchRule();
 	void optimize();
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index 07e97e0f3..0721d4fdf 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -477,7 +477,7 @@ struct ShowWorker
 			if (!design->selected_module(module->name))
 				continue;
 			if (design->selected_whole_module(module->name)) {
-				if (module->attributes.count("\\placeholder") > 0) {
+				if (module->get_bool_attribute("\\placeholder") > 0) {
 					log("Skipping placeholder module %s.\n", id2cstr(module->name));
 					continue;
 				} else
@@ -617,7 +617,7 @@ struct ShowPass : public Pass {
 		if (format != "ps") {
 			int modcount = 0;
 			for (auto &mod_it : design->modules) {
-				if (mod_it.second->attributes.count("\\placeholder") > 0)
+				if (mod_it.second->get_bool_attribute("\\placeholder") > 0)
 					continue;
 				if (mod_it.second->cells.empty() && mod_it.second->connections.empty())
 					continue;
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index e10ea4cf6..7d712d5e4 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -113,7 +113,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 
 		RTLIL::Module *mod = new RTLIL::Module;
 		mod->name = celltype;
-		mod->attributes["\\placeholder"] = RTLIL::Const(0, 0);
+		mod->attributes["\\placeholder"] = RTLIL::Const(1);
 		design->modules[mod->name] = mod;
 
 		for (auto &decl : ports) {
@@ -147,7 +147,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
 		}
 		if (cell->parameters.size() == 0)
 			continue;
-		if (design->modules.at(cell->type)->attributes.count("\\placeholder") > 0)
+		if (design->modules.at(cell->type)->get_bool_attribute("\\placeholder"))
 			continue;
 		RTLIL::Module *mod = design->modules[cell->type];
 		cell->type = mod->derive(design, cell->parameters);
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 21ef320e2..3d75b6404 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -47,7 +47,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
 				wire2driver.insert(sig, cell);
 			}
 		}
-		if (cell->type == "$memwr" || cell->attributes.count("\\keep"))
+		if (cell->type == "$memwr" || cell->get_bool_attribute("\\keep"))
 			queue.insert(cell);
 		unused.insert(cell);
 	}
diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc
index 75ca4727f..c7121959a 100644
--- a/passes/proc/proc_mux.cc
+++ b/passes/proc/proc_mux.cc
@@ -210,7 +210,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs
 	{
 		// detect groups of parallel cases
 		std::vector<int> pgroups(sw->cases.size());
-		if (sw->attributes.count("\\parallel_case") == 0) {
+		if (!sw->get_bool_attribute("\\parallel_case")) {
 			BitPatternPool pool(sw->signal.width);
 			bool extra_group_for_next_case = false;
 			for (size_t i = 0; i < sw->cases.size(); i++) {
diff --git a/passes/techmap/iopadmap.cc b/passes/techmap/iopadmap.cc
index 03d0d181c..134211e5f 100644
--- a/passes/techmap/iopadmap.cc
+++ b/passes/techmap/iopadmap.cc
@@ -144,7 +144,7 @@ struct IopadmapPass : public Pass {
 					cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
 				if (!nameparam.empty())
 					cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
-				cell->attributes["\\keep"] = RTLIL::Const();
+				cell->attributes["\\keep"] = RTLIL::Const(1);
 				module->add(cell);
 
 				wire->port_id = 0;