From: Eddie Hung Date: Wed, 4 Sep 2019 17:52:51 +0000 (-0700) Subject: Support CEM X-Git-Tag: working-ls180~1039^2~208 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e67e4a5ed66df59f5f924e6bb3891f87fc93f070;p=yosys.git Support CEM --- diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index 95105275b..4d2152f61 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -39,6 +39,7 @@ void pack_xilinx_dsp(dict &bit_to_driver, xilinx_dsp_pm &pm) log("ffB: %s\n", log_id(st.ffB, "--")); log("dsp: %s\n", log_id(st.dsp, "--")); log("ffM: %s\n", log_id(st.ffM, "--")); + log("ffMmux: %s\n", log_id(st.ffMmux, "--")); log("postAdd: %s\n", log_id(st.postAdd, "--")); log("postAddMux: %s\n", log_id(st.postAddMux, "--")); log("ffP: %s\n", log_id(st.ffP, "--")); @@ -111,11 +112,12 @@ void pack_xilinx_dsp(dict &bit_to_driver, xilinx_dsp_pm &pm) SigSpec Q = st.ffM->getPort("\\Q"); P.replace(pm.sigmap(D), Q); cell->setParam("\\MREG", State::S1); - if (st.ffM->type == "$dff") + if (st.ffMmux) { + cell->setPort("\\CEM", st.ffMmux->getPort("\\S")); + pm.autoremove(st.ffMmux); + } + else cell->setPort("\\CEM", State::S1); - //else if (st.ffP->type == "$dffe") - // cell->setPort("\\CEM", st.ffM->getPort("\\EN")); - else log_abort(); pm.autoremove(st.ffM); } if (st.ffP) { diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 8c8f431a4..9b01c22ee 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -2,9 +2,8 @@ pattern xilinx_dsp state clock state > sigAset sigBset -state sigC sigM sigMused sigP sigPused -state postAdd postAddMux -state postAddAB postAddMuxAB +state sigC sigM sigP sigPused +state ffMmuxAB postAddAB postAddMuxAB match dsp select dsp->type.in(\DSP48E1) @@ -70,22 +69,40 @@ code clock } endcode +match ffMmux + select ffMmux->type.in($mux) + select nusers(port(ffMmux, \Y)) == 2 + filter GetSize(port(ffMmux, \Y)) <= GetSize(sigM) + choice AB {\A, \B} + filter port(ffMmux, AB) == sigM.extract(0, GetSize(port(ffMmux, \Y))) + filter nusers(sigM.extract_end(GetSize(port(ffMmux, AB)))) <= 1 + set ffMmuxAB AB + optional +endmatch + +code sigM + if (ffMmux) + sigM = port(ffMmux, \Y); +endcode + match ffM if param(dsp, \MREG).as_int() == 0 select ffM->type.in($dff) // DSP48E1 does not support clock inversion select param(ffM, \CLK_POLARITY).as_bool() select nusers(port(ffM, \D)) == 2 - //index port(ffM, \D) === sigM.extract(0, GetSize(port(ffM, \D))) // TODO: Why doesn't this work!?! filter GetSize(port(ffM, \D)) <= GetSize(sigM) filter port(ffM, \D) == sigM.extract(0, GetSize(port(ffM, \D))) filter nusers(sigM.extract_end(GetSize(port(ffM, \D)))) <= 1 + // Check ffMmux (when present) is a $dff enable mux + filter !ffMmux || port(ffM, \Q) == port(ffMmux, ffMmuxAB == \A ? \B : \A) optional endmatch code clock sigM sigP if (ffM) { sigM = port(ffM, \Q); + for (auto b : sigM) if (b.wire->get_bool_attribute(\keep)) reject; @@ -97,6 +114,9 @@ code clock sigM sigP clock = c; } + // Cannot have ffMmux enable mux without ffM + else if (ffMmux) + reject; sigP = sigM; endcode @@ -108,7 +128,9 @@ match postAdd select postAdd->type.in($add) select param(postAdd, \A_SIGNED).as_bool() && param(postAdd, \B_SIGNED).as_bool() choice AB {\A, \B} - select nusers(port(postAdd, AB)) == 2 + select nusers(port(postAdd, AB)) <= 3 + filter ffMmux || nusers(port(postAdd, AB)) == 2 + filter !ffMmux || nusers(port(postAdd, AB)) == 3 filter GetSize(port(postAdd, AB)) <= GetSize(sigP) filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB))) filter nusers(sigP.extract_end(GetSize(port(postAdd, AB)))) <= 1