From: Eddie Hung <eddie@fpgeh.com>
Date: Sat, 22 Jun 2019 00:21:06 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/xaig' into xc7mux
X-Git-Tag: working-ls180~1208^2~97
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e67e78e9ac97a17d96e94c9627c1a58228e6d756;p=yosys.git

Merge remote-tracking branch 'origin/xaig' into xc7mux
---

e67e78e9ac97a17d96e94c9627c1a58228e6d756
diff --cc CHANGELOG
index 24c81be6e,fd72d5702..51ff4e1a4
--- a/CHANGELOG
+++ b/CHANGELOG
@@@ -22,11 -20,8 +22,11 @@@ Yosys 0.8 .. Yosys 0.8-de
      - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
      - Added "synth_xilinx -abc9" (experimental)
      - Added "synth_ice40 -abc9" (experimental)
+     - Added "synth -abc9" (experimental)
      - Extended "muxcover -mux{4,8,16}=<cost>"
 +    - Fixed sign extension of unsized constants with 'bx and 'bz MSB
-     - Added "synth -abc9" (experimental)
 +    - Added "muxpack" pass
 +    - "synth_xilinx" to now infer wide multiplexers (-nomux to disable)
  
  
  Yosys 0.7 .. Yosys 0.8