From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 7 Jul 2019 13:02:40 +0000 (+0100)
Subject: whitespace
X-Git-Tag: ls180-24jan2020~891
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e67f2d177f73e7246c0a44f4ddff5d0c045f479b;p=ieee754fpu.git

whitespace
---

diff --git a/src/ieee754/div_rem_sqrt_rsqrt/core.py b/src/ieee754/div_rem_sqrt_rsqrt/core.py
index c17a2be6..afc331de 100644
--- a/src/ieee754/div_rem_sqrt_rsqrt/core.py
+++ b/src/ieee754/div_rem_sqrt_rsqrt/core.py
@@ -362,9 +362,7 @@ class DivPipeCoreCalculateStage(Elaboratable):
             test = Signal(reset_less=True)
             # XXX TODO: check the width on this
             m.d.comb += test.eq((pass_flags[i] & ~next_flag))
-            m.d.comb += flag.eq(Mux(test,
-                                    trial_compare_rhs_values[i],
-                                    0))
+            m.d.comb += flag.eq(Mux(test, trial_compare_rhs_values[i], 0))
             l.append(flag)
 
         m.d.comb += next_compare_rhs.eq(Cat(*l))