From: lkcl <lkcl@web>
Date: Sun, 25 Sep 2022 00:58:16 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~296
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e68962d1a6da460f3cc65bd15d865c6464ce3b0f;p=libreriscv.git

---

diff --git a/openpower/sv/overview/discussion.mdwn b/openpower/sv/overview/discussion.mdwn
index f63980cb1..83da46cbd 100644
--- a/openpower/sv/overview/discussion.mdwn
+++ b/openpower/sv/overview/discussion.mdwn
@@ -208,6 +208,18 @@ We start with some definitions:
 * register-numbering is in **LSB0** order, prefix "r"
 * element-numbering is in **LSB0** order, prefix "e"
 
+The reasoning behind the LSB0 numbering for elements and registers
+is down to the fact that unlike a PackedSIMD Architecture which has
+fixed-width registers and fixed-size element numbering, Scalable
+Vector ISAs would require numbering element zero to be
+`VL-1` and element VL-1 to be `0` which would result in
+complete incomprehensibility.  Likewise the fact that registers
+are sequentially and serially aliases to the same underlying
+byte-addressable Memory, the register numbering must likewise
+be LSB0-ordered.  bit- and byte- numbering in MSB0 is not done
+to increase understanding: it is done to match the precedent set
+when the Power ISA was first developed, over 25 years ago.
+
 First we define the contents of 64-bit registers:
 
 | name | hi      byte/bit        | ... | lo byte/bit                     |