From: Jacob Lifshay Date: Thu, 17 Sep 2020 21:30:36 +0000 (-0700) Subject: replace sim._state.timeline.now with sim._engine.now X-Git-Tag: semi_working_ecp5~12 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e69d41220587c607be13a34cc14f917762dd529a;p=soc.git replace sim._state.timeline.now with sim._engine.now --- diff --git a/src/soc/fu/div/test/helper.py b/src/soc/fu/div/test/helper.py index 4c6bb5a7..d9c8a718 100644 --- a/src/soc/fu/div/test/helper.py +++ b/src/soc/fu/div/test/helper.py @@ -139,10 +139,10 @@ class DivTestHelper(unittest.TestCase): while not vld: yield yield Delay(0.1e-6) - # XXX sim._state is an internal variable + # XXX sim._engine is an internal variable # Waiting on https://github.com/nmigen/nmigen/issues/443 try: - print(f"time: {sim._state.timeline.now * 1e6}us") + print(f"time: {sim._engine.now * 1e6}us") except AttributeError: pass vld = yield alu.n.valid_o @@ -167,10 +167,10 @@ class DivTestHelper(unittest.TestCase): print("") yield Delay(0.1e-6) - # XXX sim._state is an internal variable + # XXX sim._engine is an internal variable # Waiting on https://github.com/nmigen/nmigen/issues/443 try: - print(f"check time: {sim._state.timeline.now * 1e6}us") + print(f"check time: {sim._engine.now * 1e6}us") except AttributeError: pass msg = "%s: %s" % (div_pipe_kind.name, code) diff --git a/src/soc/fu/div/test/test_fsm.py b/src/soc/fu/div/test/test_fsm.py index fce8418b..f18d5d7e 100644 --- a/src/soc/fu/div/test/test_fsm.py +++ b/src/soc/fu/div/test/test_fsm.py @@ -235,8 +235,8 @@ class TestDivState(unittest.TestCase): try: # FIXME(programmerjake): replace with public API # see https://github.com/nmigen/nmigen/issues/443 - now = sim._state.timeline.now - except KeyError: + now = sim._engine.now + except AttributeError: pass if divisor != 0: quotient = dividend // divisor