From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 27 Oct 2015 23:39:53 +0000 (+0100)
Subject: Improvements in new SigMap
X-Git-Tag: yosys-0.6~79
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e69efec588ddfa65b7a2d6970bab7a3bcfa77b04;p=yosys.git

Improvements in new SigMap
---

diff --git a/kernel/sigtools.h b/kernel/sigtools.h
index 3e19ac8c8..3ef87199e 100644
--- a/kernel/sigtools.h
+++ b/kernel/sigtools.h
@@ -253,18 +253,29 @@ struct SigMap
 
 		for (int i = 0; i < GetSize(from); i++)
 		{
-			RTLIL::SigBit &bf = from[i];
-			RTLIL::SigBit &bt = to[i];
+			RTLIL::SigBit bf = database.find(from[i]);
+			RTLIL::SigBit bt = database.find(to[i]);
 
-			if (bf.wire != nullptr)
+			if (bf.wire || bt.wire)
+			{
 				database.merge(bf, bt);
+
+				if (bf.wire == nullptr)
+					database.promote(bf);
+
+				if (bt.wire == nullptr)
+					database.promote(bt);
+			}
 		}
 	}
 
 	void add(RTLIL::SigSpec sig)
 	{
-		for (auto &bit : sig)
-			database.promote(bit);
+		for (auto &bit : sig) {
+			RTLIL::SigBit b = database.find(bit);
+			if (b.wire != nullptr)
+				database.promote(bit);
+		}
 	}
 
 	void apply(RTLIL::SigBit &bit) const