From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 20 Sep 2022 09:56:56 +0000 (+0100)
Subject: add sv.bc/ctr/vsb unit test to test_pysvp64dis.py to show it is possible
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e6bbdd2822bcd8ad661a89b6502e8cfa90915f8a;p=openpower-isa.git

add sv.bc/ctr/vsb unit test to test_pysvp64dis.py to show it is possible
---

diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index 981147e1..98173ba5 100644
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -256,6 +256,8 @@ class SVSTATETestCase(unittest.TestCase):
         self._do_tst(expected)
 
     def test_16_bc(self):
+        # hilarious. this should be autogenerated from a sequence
+        # of lists of options. it's a lot of frickin options.
         expected = [
                     "sv.bc/all 12,*1,0xc",
                     "sv.bc/snz 12,*1,0xc",
@@ -267,6 +269,7 @@ class SVSTATETestCase(unittest.TestCase):
                     "sv.bc/vsbi/all/snz/sl/slu/lru 12,*1,0xc",
                     "sv.bc/ctr/all/snz/sl/slu/lru 12,*1,0xc",
                     "sv.bc/cti/all/snz/sl/slu/lru 12,*1,0xc",
+                    "sv.bc/vsb/ctr/all/snz/sl/slu/lru 12,*1,0xc",
                         ]
         self._do_tst(expected)