From: rwilbur Date: Tue, 14 Sep 2021 19:43:45 +0000 (+0100) Subject: Add discussion and references for background of SVP64. X-Git-Tag: DRAFT_SVP64_0_1~135 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e6c81cf0656efb5dd3ce958cabab71ec6aa98c46;p=libreriscv.git Add discussion and references for background of SVP64. --- diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn index 5c1eab379..2f0084ce6 100644 --- a/openpower/sv.mdwn +++ b/openpower/sv.mdwn @@ -70,6 +70,98 @@ Additional links: * [[simple_v_extension]] old (deprecated) version * [[openpower/sv/llvm]] +=== + +Required Background Reading: +============================ + +These are all, deep breath, basically... required reading, *as well as and in addition* to a full and comprehensive deep technical understanding of the Power ISA, in order to understand the depth and background on SVP64 as a 3D GPU and VPU Extension. + +I am keenly aware that each of them is 300 to 1,000 pages (just like the Power ISA itself). + +This is just how it is. + +Given the sheer overwhelming size and scope of SVP64 we have gone to CONSIDERABLE LENGTHS to provide justification and rationalisation for adding the various sub-extensions to the Base Scalar Power ISA. + +* Scalar bitmanipulation is justifiable for the exact same reasons the extensions are justifiable for other ISAs. The additional justification for their inclusion where some instructions are already (sort-of) present in VSX is that VSX is not mandatory, and the complexity of implementation of VSX is too high a price to pay at the Embedded SFFS Compliancy Level. + +* Scalar FP-to-INT conversions, likewise. ARM has a javascript conversion instruction, Power ISA does not (and it costs a ridiculous 45 instructions to implement, including 6 branches!) + +* Scalar Transcendentals (SIN, COS, ATAN2, LOG) are easily justifiable for High-Performance Compute workloads. + +It also has to be pointed out that normally this work would be covered by multiple separate full-time Workgroups with multiple Members contributing their time and resources! + +Overall the contributions that we are developing take the Power ISA out of the specialist highly-focussed market it is presently best known for, and expands it into areas with much wider general adoption and broader uses. + + +--- + +OpenCL specifications are linked here, these are relevant when we get to a 3D GPU / High Performance Compute ISA WG RFC: +[[openpower/transcendentals]] + +(Failure to add Transcendentals to a 3D GPU is directly equivalent to *willfully* designing a product that is 100% destined for commercial failure.) + +I mention these because they will be encountered in every single commercial GPU ISA, but they're not part of the "Base" (core design) of a Vector Processor. Transcendentals can be added as a sub-RFC. + +--- + +Actual 3D GPU Architectures and ISAs (where such scant information is available): +--------------------------------------------------------------------------------- + +* Broadcom Videocore + + +* Etnaviv + + +* Nyuzi + + +* MALI + + +* AMD + + + +* MIAOW which is *NOT* a 3D GPU, it is a processor which happens to implement a subset of the AMDGPU ISA (Southern Islands), aka a "GPGPU" + + + +Actual Vector Processor Architectures and ISAs: +----------------------------------------------- + +* NEC SX Aurora + + +* Cray ISA + + +* RISK5 RVV + + +* MRISC32 ISA Manual (under active development) + + +* Mitch Alsup's MyISA 66000 Vector Processor ISA Manual is available from Mitch on direct contact with him. It is a different approach from the others, which may be termed "Cray-Style Horizontal-First" Vectorisation. 66000 is a *Vertical-First* Vector ISA. + +The term Horizontal or Vertical alludes to the Matrix "Row-First" or "Column-First" technique, where: + +* Horizontal-First processes all elements in a Vector before moving on to the next instruction +* Vertical-First processes *ONE* element per instruction, and requires loop constructs to explicitly step to the next element. + +Vector-type Support by Architecture +[[!table data=""" +Architecture | Horizontal | Vertical +MyISA | | X +Cray | X | +SX Aurora | X | +RVV | X | +SVP64 | X | X +"""]] + +=== + Obligatory Dilbert: