From: whitequark Date: Fri, 21 Dec 2018 04:22:16 +0000 (+0000) Subject: hdl.mem: tie rdport.en high for asynchronous or transparent ports. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e6cc3f72cf5620e90c2aebe24e995ed10b9c496c;p=nmigen.git hdl.mem: tie rdport.en high for asynchronous or transparent ports. --- diff --git a/examples/mem.py b/examples/mem.py index f966a30..1893d90 100644 --- a/examples/mem.py +++ b/examples/mem.py @@ -17,7 +17,6 @@ class RegisterFile: m.d.comb += [ rdport.addr.eq(self.adr), self.dat_r.eq(rdport.data), - rdport.en.eq(1), wrport.addr.eq(self.adr), wrport.data.eq(self.dat_w), wrport.en.eq(self.we), diff --git a/nmigen/back/verilog.py b/nmigen/back/verilog.py index 72bb83c..5c8e08d 100644 --- a/nmigen/back/verilog.py +++ b/nmigen/back/verilog.py @@ -27,11 +27,9 @@ proc_init proc_arst proc_dff proc_clean -design -save orig memory_collect write_verilog # Make sure there are no undriven wires in generated RTLIL. -design -load orig proc select -assert-none w:* i:* %a %d o:* %a %ci* %d c:* %co* %a %d n:$* %d """.format(il_text)) diff --git a/nmigen/hdl/mem.py b/nmigen/hdl/mem.py index 3091890..b6aacb7 100644 --- a/nmigen/hdl/mem.py +++ b/nmigen/hdl/mem.py @@ -28,8 +28,8 @@ class Memory: self.depth = depth self.init = None if init is None else list(init) - def read_port(self, domain="sync", asynchronous=False, transparent=True): - return ReadPort(self, domain, asynchronous, transparent) + def read_port(self, domain="sync", synchronous=False, transparent=True): + return ReadPort(self, domain, synchronous, transparent) def write_port(self, domain="sync", priority=0, granularity=None): if granularity is None: @@ -42,22 +42,25 @@ class Memory: class ReadPort: - def __init__(self, memory, domain, asynchronous, transparent): - self.memory = memory - self.domain = domain - self.asynchronous = asynchronous - self.transparent = transparent + def __init__(self, memory, domain, synchronous, transparent): + self.memory = memory + self.domain = domain + self.synchronous = synchronous + self.transparent = transparent self.addr = Signal(max=memory.depth) self.data = Signal(memory.width) - self.en = Signal() + if synchronous and transparent: + self.en = Signal() + else: + self.en = Const(1) def get_fragment(self, platform): return Instance("$memrd", p_MEMID=self.memory, p_ABITS=self.addr.nbits, p_WIDTH=self.data.nbits, - p_CLK_ENABLE=not self.asynchronous, + p_CLK_ENABLE=self.synchronous, p_CLK_POLARITY=1, p_TRANSPARENT=self.transparent, i_CLK=ClockSignal(self.domain),