From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 7 Aug 2019 18:11:50 +0000 (-0700)
Subject: Merge remote-tracking branch 'origin/master' into eddie/cleanup
X-Git-Tag: working-ls180~1151^2~3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e6d5147214bd157c457654dc46547775ec6ad324;p=yosys.git

Merge remote-tracking branch 'origin/master' into eddie/cleanup
---

e6d5147214bd157c457654dc46547775ec6ad324
diff --cc passes/opt/opt_expr.cc
index ef4b8b57a,acdc39937..b2dc9a448
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@@ -640,10 -641,38 +640,35 @@@ void replace_const_cells(RTLIL::Design 
  					did_something = true;
  				}
  			}
+ 
+ 			if (cell->type.in("$add", "$sub")) {
+ 				RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
+ 				RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B"));
+ 				RTLIL::SigSpec sig_y = cell->getPort("\\Y");
+ 				bool sub = cell->type == "$sub";
+ 
+ 				int i;
+ 				for (i = 0; i < GetSize(sig_y); i++) {
+ 					if (sig_b.at(i, State::Sx) == State::S0 && sig_a.at(i, State::Sx) != State::Sx)
+ 						module->connect(sig_y[i], sig_a[i]);
+ 					else if (!sub && sig_a.at(i, State::Sx) == State::S0 && sig_b.at(i, State::Sx) != State::Sx)
+ 						module->connect(sig_y[i], sig_b[i]);
+ 					else
+ 						break;
+ 				}
+ 				if (i > 0) {
+ 					cover_list("opt.opt_expr.fine", "$add", "$sub", cell->type.str());
+ 					cell->setPort("\\A", sig_a.extract_end(i));
+ 					cell->setPort("\\B", sig_b.extract_end(i));
+ 					cell->setPort("\\Y", sig_y.extract_end(i));
+ 					cell->fixup_parameters();
+ 					did_something = true;
+ 				}
+ 			}
  		}
  
 -		if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" || cell->type == "$shift" || cell->type == "$shiftx" ||
 -				cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr" ||
 -				cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt" ||
 -				cell->type == "$neg" || cell->type == "$add" || cell->type == "$sub" ||
 -				cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod" || cell->type == "$pow")
 +		if (cell->type.in("$reduce_xor", "$reduce_xnor", "$shift", "$shiftx", "$shl", "$shr", "$sshl", "$sshr",
 +					"$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow"))
  		{
  			RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
  			RTLIL::SigSpec sig_b = cell->hasPort("\\B") ? assign_map(cell->getPort("\\B")) : RTLIL::SigSpec();