From: Andrew Zonenberg <azonenberg@drawersteak.com>
Date: Tue, 15 Aug 2017 07:50:31 +0000 (-0700)
Subject: Fixed more issues with GreenPAK counter sim models
X-Git-Tag: yosys-0.8~344^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e6eaf487b6d46804641c67325082210e6f3d6d64;p=yosys.git

Fixed more issues with GreenPAK counter sim models
---

diff --git a/techlibs/greenpak4/cells_sim_digital.v b/techlibs/greenpak4/cells_sim_digital.v
index 6fba941a0..043cd18d4 100644
--- a/techlibs/greenpak4/cells_sim_digital.v
+++ b/techlibs/greenpak4/cells_sim_digital.v
@@ -58,23 +58,25 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 
 			"RISING": begin
 				always @(posedge CLK, posedge RST) begin
-					count		<= count - 1'd1;
-					if(count == 0)
-						count	<= COUNT_TO;
-
 					if(RST)
-						count	<= 0;
+						count		<= 0;
+					else begin
+						count		<= count - 1'd1;
+						if(count == 0)
+							count	<= COUNT_TO;
+					end
 				end
 			end
 
 			"FALLING": begin
 				always @(posedge CLK, negedge RST) begin
-					count		<= count - 1'd1;
-					if(count == 0)
-						count	<= COUNT_TO;
-
 					if(!RST)
-						count	<= 0;
+						count		<= 0;
+					else begin
+						count		<= count - 1'd1;
+						if(count == 0)
+							count	<= COUNT_TO;
+					end
 				end
 			end
 
@@ -88,7 +90,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
 			"LEVEL": begin
 				always @(posedge CLK, posedge RST) begin
 					if(RST)
-						count	<= 0;
+						count		<= 0;
 
 					else begin
 						count		<= count - 1'd1;
@@ -422,23 +424,25 @@ module GP_COUNT8(
 
 			"RISING": begin
 				always @(posedge CLK, posedge RST) begin
-					count		<= count - 1'd1;
-					if(count == 0)
-						count	<= COUNT_TO;
-
 					if(RST)
 						count	<= 0;
+					else begin
+						count		<= count - 1'd1;
+						if(count == 0)
+							count	<= COUNT_TO;
+					end
 				end
 			end
 
 			"FALLING": begin
 				always @(posedge CLK, negedge RST) begin
-					count		<= count - 1'd1;
-					if(count == 0)
-						count	<= COUNT_TO;
-
 					if(!RST)
 						count	<= 0;
+					else begin
+						count		<= count - 1'd1;
+						if(count == 0)
+							count	<= COUNT_TO;
+					end
 				end
 			end