From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 11 Nov 2021 15:51:39 +0000 (+0000)
Subject: enable hazard vecs in core
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e6fca060bde84ea0e06dfddc23f41c9fad04701e;p=soc.git

enable hazard vecs in core
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index 0602691b..0a000bf7 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -149,6 +149,11 @@ class NonProductionCore(ControlBase):
         self.regreduce_en = (hasattr(pspec, "regreduce") and
                              (pspec.regreduce == True))
 
+        # test core type
+        self.core_type = "fsm"
+        if hasattr(pspec, "core_type":
+            self.core_type = pspec.core_type
+
         super().__init__(stage=self)
 
         # single LD/ST funnel for memory access
@@ -168,7 +173,7 @@ class NonProductionCore(ControlBase):
             mmu.alu.set_ldst_interface(l0.cmpi.lsmem.lsi)
 
         # register files (yes plural)
-        self.regs = RegFiles(pspec)
+        self.regs = RegFiles(pspec, make_hazard_vecs=True)
 
         # set up input and output: unusual requirement to set data directly
         # (due to the way that the core is set up in a different domain,