From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 24 May 2020 18:48:21 +0000 (+0100)
Subject: add missing OP_MFMSR and OP_MTMSRD
X-Git-Tag: convert-csv-opcode-to-binary~2571
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e703c2a52d8fc9015e18b10936f75ffb3ff17d3f;p=libreriscv.git

add missing OP_MFMSR and OP_MTMSRD
---

diff --git a/openpower/isatables/minor_31.csv b/openpower/isatables/minor_31.csv
index 4cf4f40a4..a2755805e 100644
--- a/openpower/isatables/minor_31.csv
+++ b/openpower/isatables/minor_31.csv
@@ -105,12 +105,14 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0b1000000000,,,,,,,,,,,,,,,,,,,,,,,mcrxr,X
 0b1001000000,,,,,,,,,,,,,,,,,,,,,,,mcrxrx,X
 0b0000010011,CR,OP_MFCR,NONE,NONE,NONE,RT,WHOLE_REG,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mfcr/mfocrf,XFX
+0b0001010011,ALU,OP_MFMSR,NONE,NONE,NONE,RT,NONE,0,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mfmsr,X
 0b0101010011,ALU,OP_MFSPR,SPR,NONE,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mfspr,XFX
 0b0100001001,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,modud,X
 0b0100001011,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,0,NONE,0,0,moduw,X
 0b1100001001,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,1,NONE,0,0,modsd,X
 0b1100001011,DIV,OP_MOD,RA,RB,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,1,1,NONE,0,0,modsw,X
 0b0010010000,CR,OP_MTCRF,NONE,NONE,RS,NONE,WHOLE_REG,WHOLE_REG,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtcrf/mtocrf,XFX
+0b0010110010,ALU,OP_MTMSRD,NONE,NONE,RS,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,mtmsrd # ignore top bits and d,X
 0b0111010011,ALU,OP_MTSPR,NONE,NONE,RS,SPR,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,mtspr,XFX
 0b0001001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,1,RC,0,0,mulhd,XO
 0b0000001001,MUL,OP_MUL_H64,RA,RB,NONE,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,mulhdu,XO