From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 29 Mar 2022 19:43:10 +0000 (+0100)
Subject: add bus.err to list of default Wishbone signals in Tercel
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e71dc3c11a1085aa609833a4a3c2eecd2f18876e;p=soc.git

add bus.err to list of default Wishbone signals in Tercel
---

diff --git a/src/soc/bus/tercel.py b/src/soc/bus/tercel.py
index bbf7cfe6..10221823 100644
--- a/src/soc/bus/tercel.py
+++ b/src/soc/bus/tercel.py
@@ -50,7 +50,7 @@ class Tercel(Elaboratable):
 
         # set up the wishbone busses
         if features is None:
-            features = frozenset()
+            features = frozenset({'err'})
         if bus is None:
             bus = Interface(addr_width=spi_region_addr_width,
                             data_width=data_width,
@@ -138,6 +138,7 @@ class Tercel(Elaboratable):
                             i_wishbone_stb=bus.stb,
                             i_wishbone_cyc=bus.cyc,
                             o_wishbone_ack=bus.ack,
+                            o_wishbone_err=bus.err,
 
                             # Configuration region Wishbone bus signals
                             i_cfg_wishbone_adr=cfg_bus.adr,
@@ -148,6 +149,7 @@ class Tercel(Elaboratable):
                             i_cfg_wishbone_stb=cfg_bus.stb,
                             i_cfg_wishbone_cyc=cfg_bus.cyc,
                             o_cfg_wishbone_ack=cfg_bus.ack,
+                            o_cfg_wishbone_err=cfg_bus.err,
 
                             # QSPI signals
                             o_spi_d_out=self.dq_out,