From: lkcl <lkcl@web>
Date: Sat, 23 Jul 2022 10:50:28 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1096
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e726123a2152c5aa3ed51b2e3accfa6cbf358acd;p=libreriscv.git

---

diff --git a/openpower/sv/executive_summary.mdwn b/openpower/sv/executive_summary.mdwn
index 7ff6d1f51..304f63a6c 100644
--- a/openpower/sv/executive_summary.mdwn
+++ b/openpower/sv/executive_summary.mdwn
@@ -18,8 +18,11 @@ the provision of a `setvl` instruction and why they are each called
 presents the programmer with explicit control over Vector length.
 
 ARM NEON, AVX-512 and ARM SVE2 are all Predicated SIMD ISAs and
-**do not provide Scalability**. Programmers must emulate scaling
-through explicit predicate masks which increases instruction count in
+**do not provide Scalability to the Programmer** (SVE2 is **Silicon**
+Scalable, not **Programmer** Scalable: the distinction is profoundly
+critical).
+For Predicated SIMD, Programmers must emulate scaling
+through explicit predicate masking, which increases instruction count in
 hot-loops.
 
 We invented Simple-V to be simple because we don't like complicated.