From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 7 Aug 2013 16:39:49 +0000 (+0200)
Subject: Improved handling of private names in opt_clean and rename commands
X-Git-Tag: yosys-0.2.0~517
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=e7298576479eadf0a40c1c244d67e98b3238262f;p=yosys.git

Improved handling of private names in opt_clean and rename commands
---

diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc
index 906256a1c..a582de56d 100644
--- a/passes/cmds/rename.cc
+++ b/passes/cmds/rename.cc
@@ -63,6 +63,12 @@ struct RenamePass : public Pass {
 		log("Rename the specified object. Note that selection patterns are not supported\n");
 		log("by this command.\n");
 		log("\n");
+		log("\n");
+		log("    rename -enumerate [selection]\n");
+		log("\n");
+		log("Assign short auto-generated names to all selected wires and cells with private\n");
+		log("names.\n");
+		log("\n");
 	}
 	virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
 	{
@@ -72,17 +78,43 @@ struct RenamePass : public Pass {
 		for (argidx = 1; argidx < args.size(); argidx++)
 		{
 			std::string arg = args[argidx];
-			//if (arg == "-enumerate") {
-			//	flag_enumerate = true;
-			//	continue;
-			//}
+			if (arg == "-enumerate") {
+				flag_enumerate = true;
+				continue;
+			}
 			break;
 		}
 
 		if (flag_enumerate)
 		{
 			extra_args(args, argidx, design);
-			log_cmd_error("Sorry: Enumeration mode is not implemented at the moment.\n");
+
+			for (auto &mod : design->modules)
+			{
+				int counter = 0;
+
+				RTLIL::Module *module = mod.second;
+				if (!design->selected(module))
+					continue;
+
+				std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
+				for (auto &it : module->wires) {
+					if (it.first[0] == '$' && design->selected(module, it.second))
+						do it.second->name = stringf("\\_%d_", counter++);
+						while (module->count_id(it.second->name) > 0);
+					new_wires[it.second->name] = it.second;
+				}
+				module->wires.swap(new_wires);
+
+				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
+				for (auto &it : module->cells) {
+					if (it.first[0] == '$' && design->selected(module, it.second))
+						do it.second->name = stringf("\\_%d_", counter++);
+						while (module->count_id(it.second->name) > 0);
+					new_cells[it.second->name] = it.second;
+				}
+				module->cells.swap(new_cells);
+			}
 		}
 		else
 		{
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 983e5d5fa..c6ca8c25a 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -122,10 +122,10 @@ static bool check_public_name(RTLIL::IdString id)
 {
 	if (id[0] == '$')
 		return false;
-#if 0
+	if (id.substr(0, 2) == "\\_" && (id[id.size()-1] == '_' || id.find("_[") != std::string::npos))
+		return false;
 	if (id.find(".$") != std::string::npos)
 		return false;
-#endif
 	return true;
 }